Jasper’s DAC Program

Jasper’s DAC Program
by Paul McLellan on 05-28-2013 at 3:52 pm

Jasper’s booth is 2346 where you can see demos of the JasperGold Apps and attend seminars on the experiences of ST and Broadcom, and others:

  • The Broadcom presentation on making formal an integral part of chip design is Tuesday at 10am.
  • The ST presentation on adapting formal methods in ARM subsystems is Monday at 1.30pm and
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Jasper Low Power Verification App

Jasper Low Power Verification App
by Paul McLellan on 05-14-2013 at 1:58 am

Today, Jasper announced their new Jasper-Gold Low Power Verification App. This is focused on verifying low power designs with multiple power domains, voltage islands, power shutoff, clock shutoff, and all the other techniques used for reducing power. Of course power is the main driver of SoC design these days, whether it is for… Read More


Kathryn Kranen Joins CriticalBlue’s Board

Kathryn Kranen Joins CriticalBlue’s Board
by Paul McLellan on 05-02-2013 at 8:05 pm

Jasper just announced that Kathryn Kranen, their CEO, had joined the board of CriticalBlue. I used it as an excuse to hit up CriticalBlue’s CEO Dave Stewart, who happened to be in the valley, for a free lunch to catch up on what they are doing.

CriticalBlue started about 10 years ago in Edinburgh (yay!). When it started it was in the business… Read More


Atrenta, Forte and Jasper LOVE DAC

Atrenta, Forte and Jasper LOVE DAC
by Paul McLellan on 04-16-2013 at 8:20 pm

I LOVE DAC is back. This year the sponsors are Atrenta, Jasper and Forte (hey, all semiwiki subscribers). The way it works is that you register on the DAC website here and you get a free three-day exhibit pass. In addition to everything going on in the exhibit hall, including the pavilion panels held there, the pass also gives access… Read More


Kathryn Kranen Wins UBM Lifetime Achievement Award 2013

Kathryn Kranen Wins UBM Lifetime Achievement Award 2013
by Paul McLellan on 04-03-2013 at 6:54 pm

UBM’s EETimes and EDN today announced Kathryn Kranen as the lifetime achievement award winner for this years ACE awards program. Kathryn, of course, is the CEO of Jasper (and is also currently the chairman of EDAC). Past winners exemplify the prestige and significance of the award. Since 2005 the award was given to Gordon… Read More


Formal Verification of Power Intent

Formal Verification of Power Intent
by Paul McLellan on 03-13-2013 at 4:10 pm

I can’t imagine that any SoC today is designed without taking intense interest in how much power the chip will consume, whether it is destined for a mobile phone or tethered in a cloud datacenter. One challenge with power is that adding features like voltage islands or power-down areas require changes to the netlist such as… Read More


Cavium Adopts JasperGold Architectural Modeling

Cavium Adopts JasperGold Architectural Modeling
by Paul McLellan on 03-05-2013 at 7:00 am

Cavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.

Cavium have… Read More


Catch Jasper at SemiIsrael Verification Day and at DVCon 2013

Catch Jasper at SemiIsrael Verification Day and at DVCon 2013
by Paul McLellan on 01-30-2013 at 4:08 pm

Jasper is presenting at both ends of the world at both ends of February.

First in Israel, it is SemiIsrael Verification Day 2013 on February 5th (next Tuesday) at Green House in Tel Aviv.

  • Zihad Hanna, VP of Research and Chief Architect and General Manager of Jasper Israel will be talking about Security Formal Verification of Hardware
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Formal Verification at ARM

Formal Verification at ARM
by Paul McLellan on 12-20-2012 at 4:34 pm

There are two primary microprocessor companies in the world these days: Intel and ARM. Of course there are many others but Intel is dominant on the PC desktop (including Macs) and ARM is dominant in mobile (including tablets).

One of the keynotes at last month’s Jasper User Group (JUG, not the greatest of acronyms) was by Bob… Read More


Formal Analysis of Security Data Paths

Formal Analysis of Security Data Paths
by Paul McLellan on 12-05-2012 at 5:07 pm

One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More