The three-step conversational AI (CAI) process – automatic speech recognition (ASR), natural language processing, and text-to-synthesized speech response – is now deeply embedded in the user experience for smartphones, smart speakers, and other devices. More powerful large language models (LLMs) can answer more queries… Read More
Tag: fpga acceleration
Scaling LLMs with FPGA acceleration for generative AI
Large language model (LLM) processing dominates many AI discussions today. The broad, rapid adoption of any application often brings an urgent need for scalability. GPU devotees are discovering that where one GPU may execute an LLM well, interconnecting many GPUs often doesn’t scale as hoped since latency starts piling up with… Read More
Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
Before starting your next FPGA Prototyping Project you should catch the next SemiWiki webinar – “Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards”, in partnership with Aldec.
A significant portion of my 30+ years in the EDA industry has revolved around design verification with some form of FPGA … Read More
Achronix Announces New Accelerator Card at Linley Fall Processor Conference – VectorPath
This blog is my second blog from this year’s Linley Fall Processor Conference. The first two blogs focused on edge inference solutions. Achronix’s discussion was much broader than just AI/ML; it was about where FPGA’s have been going and culminated with a product announcement preview. I’ll get to the announcement in a moment, … Read More
Fantasy Tech-Ball and the Intel Rumor Wire
Reading Intel analysis lately has been a lot like reading fantasy baseball analysis. Intel should buy Altera. Intel should waive Atom. Intel should fab for Apple. All of those have a near-zero probability of happening IMHO, and yet pundits continue to pitch their version of alternate reality, dealing away product lines and strategies… Read More