Daniel,
On Jan 20th, you criticized that the EDA models are all broken and need to change. Ridiculing Synpsys, Cadence, Mentor and Magma for not agreeing to ‘pay for success’ type of model (some form of royalties).
On Feb 14th, you state thatIcahn doesn’t understand EDA and should stay out. Maybe he is seeing … Read More
San Jose, Calif., [DATE], 2011 – SemiWiki.com today announced that Mentor Graphics, a world leader in electronic hardware and software design solutions, will participate in the SemiWiki.com global social media platform aimed at facilitating mass communication for electronic design professionals through Web 2.0 technologies.… Read More
There has been a lot of talk about the fluid role of IP in semiconductor design. With the Synopsys acquisition of Virage Logic the playing field has tilted substantially in favor of Synopsys… or maybe not!
At first glance this acquisition appears to be a huge threat to EDA and IP companies allowing Synopsys to “throw in” IP as… Read More
A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan
Today’s IC designs are complex. They contain vast arrays of features and functionality in … Read More
Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already… Read More
When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor:… Read More
"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO
Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address … Read More
I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.
In the old days each foundry would have to staff up… Read More
Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.
Sudhakar Jilla,… Read More
I met Ian Getreu in Oregon at a monthly EDA networking luncheon several years ago and have kept in touch with him. Ian co-founded Analogy which was later acquired by Avant! (now Synopsys). One thing that Ian noticed over the years was that smaller EDA companies were constantly getting acquired by the bigger and publicly traded EDA… Read More
