Design Test and Regression Management of SoCs

Design Test and Regression Management of SoCs
by Daniel Payne on 06-28-2013 at 2:26 pm

Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.


Eric Peers, MethodicsRead More


HW Prototyping and HLS at DAC

HW Prototyping and HLS at DAC
by Daniel Payne on 06-28-2013 at 12:20 pm

I love it when EDA companies send their engineers to DAC because I learn more of the unvarnished truth about their products. I met with Bill Thomas of Aldec to get an update on their HW prototyping boards, then two NEC engineers to learn about High Level Synthesis.

HW Prototyping

Bill Thomas, Research Engineer at Aldec
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A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis

A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis
by Daniel Payne on 06-27-2013 at 2:38 pm

The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.


Dermott Lynch,Read More


Aart: Technomic Push-Pull

Aart: Technomic Push-Pull
by Paul McLellan on 06-26-2013 at 11:00 pm

Aart de Geus gave one of the visionary look to the next 50 years of EDA as a warmup to Stephen Wu’s keynote. EDA is enabling the greatest push-pull ever, part of an exponential change on a scale never before seen.

Technologies seem to go through a 50 year technical push phase (driven by improving the technology) followed by a 50… Read More