Real FPGAs don’t eat fake test vectors

Real FPGAs don’t eat fake test vectors
by Don Dingee on 06-26-2014 at 8:00 am

Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot… Read More


If requirements ask for it, it had better be there

If requirements ask for it, it had better be there
by Don Dingee on 01-29-2014 at 8:00 pm

Engineers are known for their attention to detail and precision in thinking, but sometimes still struggle during compliance audits. This is especially true the longer a list of requirements becomes, especially unstructured lists kept in spreadsheets and on Post-It notes.

It gets even more complicated, because in defense circles… Read More