It is a well-known fact that chiplets provide several advantages over traditional monolithic chips. Despite these benefits, the transition to a chiplet-based design paradigm presents challenges that need coordinated efforts across the industry. In essence, collaborative efforts among various players involved are not … Read More
Tag: chiplet
The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More
Chiplet Summit 2025
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Blue Cheetah Advancing Chiplet Interconnectivity #61DAC
At #61DAC, I love it when an exhibitor booth uses a descriptive tagline to explain what they do, like when the Blue Cheetah booth displayed Advancing Chiplet Interconnectivity. Immediately, I knew that they were an IP provider focusing on chiplets. I learned what sets them apart is how customizable their IP is to support specific… Read More
Keysight EDA at the 2024 Design Automation Conference
DAC starts June 24th and I can already feel the buzz of excitement building up as I receive updates from EDA vendors like Keysight EDA. Talking with Scott Seiden, Director Strategic Marketing, Keysight EDA Portfolio, I learned that they have the largest booth on the first floor, now that’s a statement that caught my attention. This… Read More
AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
Artificial Intelligence (AI) continues to revolutionize industries, from healthcare and finance to automotive and manufacturing. AI applications, such as machine learning, deep learning, and neural networks, rely on vast amounts of data for training, inference, and decision-making processes. As AI algorithms become … Read More
Alphawave Semi Bridges from Theory to Reality in Chiplet-Based AI
GenAI, the most talked-about manifestation of AI these days, imposes two tough constraints on a hardware platform. First, it demands massive memory to serve large language model with billions of parameters. Feasible in principle for a processor plus big DRAM off-chip and perhaps for some inference applications but too slow … Read More
2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification
2024 DVCon was very busy this year. Bernard Murphy and I were in attendance for SemiWiki, he has already written about it. Multi die and chiplets was again a popular topic. Lauro Rizzatti, a consultant specializing in hardware-assisted verification, moderated an engaging panel, sponsored by Synopsys, focusing on the intricacies… Read More
How MZ Technologies is Making Multi-Die Design a Reality
The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply… Read More
ESD Alliance and Silicon Assurance Host Industry Panel Discussion on Chiplet Security
Security threats are a hot topic of discussion today as they can have a profound impact on the electronic infrastructure and devices that are the backbone of our global economies. It is also clear that these threats can be introduced during the design of the very devices that we rely on in our daily lives.
Chiplet-based design is … Read More