SoC projects are running behind schedule as design and verification complexity has increased dramatically, so just adding more engineers, more tests and more compute aren’t the answer. The time is ripe to consider smarter ways to improve verification efficiency. The added complexity of multiple embedded processors, multiple… Read More
Tag: asic
Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business
The second chapter of our book “Fabless: The Transformation of Semiconductor Industry” describes the ASIC business and how important it is. That was more than 10 years ago and the ASIC business is still at the forefront of the Semiconductor industry and is a key enabler of the AI revolution we are experiencing today.
First let’s … Read More
WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.
The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More
Webinar: Functional ECO Solution for Mixed-Signal ASIC Design
Functional ECO (Engineering Change Order) continues to pose a persistent challenge for ASIC designers. To address this, Easy-Logic Technology, in collaboration with SemiWiki, is launching a webinar series focused on tackling ECO challenges across various ASIC design segments—starting with Mixed-Signal ASICs.
Why Mixed-Signal
… Read MoreArchitecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem Realities
Designing a system-on-chip (SoC) has never been more complex—or more critical. With accelerating demands across AI, automotive, and high-performance compute applications, today’s SoC architects face a series of high-stakes tradeoffs from the very beginning. Decisions made during the earliest phases of design—regarding… Read More
Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells
Dan is joined by sureCore CEO Paul Wells. Paul has worked in the semiconductor industry for over 25 years including two years as director of engineering for Pace Networks, where he led a multidisciplinary, 70 strong product development team creating a broadcast quality video & data mini-headend. Before that, he worked for… Read More
AI Booming is Fueling Interface IP 23.5% YoY Growth
AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system need to be interconnected with ever more bandwidth and lower latency, creating the need for ever advanced protocol… Read More
WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More
Easylogic at the 2025 Design Automation Conference #62DAC
EasylogicECO Provides Built-In Stage-Based Functional ECO Flows to Reduce Turnaround Time
HONG KONG — June 6, 2025 — EasyLogic proudly introduces a groundbreaking stage-based ECO design environment, built into the EasylogicECO tool, to meet the rapidly evolving functional ECO (Engineering Change Order) demands of today’s… Read More
