Aldec and Tanner EDA at DAC

Aldec and Tanner EDA at DAC
by Daniel Payne on 05-18-2012 at 10:19 am

In April I blogged about a webinar on co-simulation hosted by Aldec and Tanner EDA where they showed how the RTL simulator (Riviera PRO) and SPICE simulator (T-Spice) had been connected together for IC designers wanting to do real AMS simulations.

The availability date of the co-simulation wasn’t clear, so today the pressRead More


AMS Design using Co-Simulation

AMS Design using Co-Simulation
by Daniel Payne on 04-23-2012 at 11:13 am

The big three vendors in EDA offer AMS simulation tools but what about simulation choices from other EDA vendors?

It turns out there are two privately held EDA companies that have done business since the 1980’s and have just integrated a Verilog A simulator with a SPICE circuit simulator. The two companies are Aldec with a … Read More


Learning Verilog for ASIC and FPGA Design

Learning Verilog for ASIC and FPGA Design
by Daniel Payne on 11-02-2011 at 11:17 am

Verilog History
Prabhu Goel founded Gateway Design Automation and Phil Moorby wrote the Verilog language back in 1984. In 1989 Cadence acquired Gateway and Verilog grew into a de-facto HDL standard. I first met Prabu at Wang Labs in 1982 where I designed a rather untestable custom chip named the WL-2001 (yes, it was named to honor… Read More