It’s been a bit more than a year since I interviewed Dr. Ashish Darbari, founder and CEO of Axiomise. I’ve been keeping an eye on Ashish and his colleagues, and I was surprised to learn that they recently celebrated their fifth anniversary as a company. I thought that this would be a good time to catch up with him to find out what’s happened over the year since we talked and to learn more about the last five years.
Ashish, congratulations on reaching five years! Can you summarize your journey?
Thank you, Dan. If I had to pick just one word, it would be “amazing.” When I set up Axiomise in October 2017 to offer training and consulting services around formal verification, it was because I knew that there was a big hole in the available industry solutions and methodologies, and therefore a big need and a big opportunity. But I have to say that the past five years have met or exceeded every expectation that I had. Clients have responded enthusiastically and provided us the business to grow and prosper. I’m very grateful for their support, and for the interest that you and others in the EDA community have shown in our company.
How has Axiomise evolved since we last spoke?
2022 has been incredible for us. For a start, we’ve been growing as a company. Gurudutt (GD) Bansal joined as COO and Neil Dunlop joined as CTO. They’ve been great partners in taking our business to the next level. We opened new offices in Hemel Hempstead, just outside of London, with room for more team members going forward.
I see on Wikipedia that Hemel Hempstead has been a village for more than 1000 years and was granted its town charter by Henry VIII in 1539. So you’re part of that great European tradition of doing cutting-edge technical work in historic settings?
That’s a nice way to look at it. The U.K. is a great location for a services company. We can work with Asia in our morning, with North America in our afternoon, and with Europe all day. We have a worldwide client base, which is part of our amazing story.
Speaking of expanding your scope, I see that you recently joined the ESD Alliance. What role will that play in your future?
As part of the SEMI Technology community, the ESD Alliance is closely tied to the semiconductor industry, and that’s where our clients are. So we’re becoming a more integral part of the chip ecosystem and are already networking, making contacts, and forging relationships that will help us grow further. The benefits of membership work both ways. The ESD Alliance is the voice of the EDA industry, and we feel that any successful company should be part of it and give back to the community by sharing experiences and offering advice to fellow members.
One of the things that has impressed me about you personally is your ability to act as an industry spokesperson for formal while running a company and doing hands-on verification work. Have you continued your speaking activity in 2022?
My goodness, yes. It’s been a really busy year on that front. Probably my highest profile activity was participating in the panel “Those Darn Bugs” at the Design Automation Conference (DAC) in San Francisco. Brian Bailey of Semiconductor Engineering led a lively discussion on whether it will ever be possible to eradicate all bugs from chip designs. Of course, there is no chance of that happening without formal taking a lead role. A video of the panel is available online and I think it’s worth watching.
Also at DAC, I talked about “Taming the Beast: RISC-V Formal Verification Made Easy” in the Cadence Theatre. I explained how 32-bit and 64-bit processors cores are verified with formal verification using the Axiomise formalISA app. A video of this talk is also available. Please thank your colleague Daniel Payne for covering our DAC activities.
I joined the “SoC Leaders Verify with Synopsys” panel at the Synopsys Users Group (SNUG) event and a recording of that is online as well. At DVCon Europe in Munich, I appeared on the panel “5G Chip Design Challenges and their Impact on Verification.” Also in Munich, I presented “Accelerating Debug and Signoff for RISC-V Processors Using Formal Verification” at CadenceLIVE Europe. Finally, I discussed how formal can address safety and security as well as functional verification at a Cadence Club Formal event in the U.K.
The Axiomise team participates in all kinds of events. Thanks to your colleague GD for doing a podcast with me earlier this year. The immediacy and directness of a podcast seemed to work well for explaining the potentially scary topic of formal. Have you done others?
I had the pleasure of recording a “Fish Fry” with Amelia Dalton of EE Journal on “The Art of Predictability” and the three pillars of formal verification. In fact, I like podcasts so much that I have my own series and have now recorded 50 episodes.
That’s really impressive; I can’t imagine how you possibly find the time. You write quite a bit as well, don’t you?
Yes, this year, I’ve published articles in EDN magazine and Electronic Design magazine. We also do webinars, white papers, and more. You can go to the Knowledge Hub menu on our website to get a complete list.
Surely all this external activity doesn’t prevent you from continuing to innovate in formal?
Not a chance. Speaking and writing is fun, but it’s the work with our clients that keeps us in business. They’re designing and verifying some of the biggest and baddest chips in the world, so they are constantly pushing the limits of formal technology. We have no choice but to innovate constantly, and that’s a big part of the value we bring to the industry.
As you can see from some of our talks and articles, our biggest innovation this year was expanding our solution for RISC-V verification. We announced this late last year and since then have been very busy helping clients verify their processors. Again and again, we have found serious bugs in RISC-V designs when they were thought to be correct based on massive amounts of simulation testing and even, in some cases, had been fabricated and tested in silicon.
How do you work with your clients?
Our primary goal is to offer maximum ROI to the client in the shortest possible time. It often means we take the formal verification work hands-on as a turnkey services project. It allows the client to see how formal is done on actual designs at a fast pace with excellent proof convergence finding bugs and establishing proofs of bug absence. Apart from the turnkey services work, which has been our primary focus, we also offer training to complement the services.
Do you have any final thoughts for our readers?
I just want to thank everyone who has provided support to us for the last five years. We’re excited to have hit this milestone but it’s only the beginning of what we can do to lead the industry in creating chips that are functionally correct, safe, and secure. To lean more, you can email us at info@axiomise.com or contact us through www.axiomise.com. We are here to help.
Thank you for your time, Ashish.
You’re most welcome!
Also Read:
CEO Interview: Dr. Ashish Darbari of Axiomise
Accelerating Exhaustive and Complete Verification of RISC-V Processors
Life in a Formal Verification Lane
Why I made the world’s first on-demand formal verification course
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