A Brief History of TSMC

A Brief History of TSMC
by Daniel Nenni on 08-02-2012 at 7:30 pm

In 1985 Morris Chang was recruited by the Taiwanese government to help develop the emerging semiconductor industry. In 1986 Morris joined the Hsinchu based non profit research institute ITRI as Chairman and President and launched what would be TSMC’s first semiconductor wafer fabrication plant on the ITRI campus. Taiwan Semiconductor Manufacturing Company Ltd. was officially formed in 1987 as a joint venture between the Taiwan government (21%), Dutch multinational electronics giant Philips (28%), and other private investors.

Without a doubt, TSMC created what is today’s semiconductor foundry business model. While at TI, Morris Chang pioneered the then controversial idea of pricing semiconductors ahead on the cost curve, sacrificing early profits to gain market share to achieve manufacturing yields that would result in greater long-term profits. This pricing model is still the foundation of the fabless semiconductor business model.

Even starting 2 process nodes behind competing semiconductor manufacturers (IDMs), TSMC was able to attract customers. 4-5 years later TSMC was only behind 1 process node and the orders started pouring in. In 10 years TSMC caught up with IDMs and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing. Today TSMC is the undisputed leader with a reported 49% share of the $30B foundry market segment. UMC is second with just over a 12% share, GlobalFoundries is a close third with 12%, and SMIC is fourth with 4.4%.

As the story goes, Morris Chang made the first TSMC sales calls in 1987 with a single brochure:

TSMC Core Values: Integrity, commitment, innovation, and customer trust.

It is interesting to compare the consistency of this statement with the 1997 TSMC mission statement:

We are building the world’s Virtual Fab! We provide the best quality technology, the greatest capacity and the highest standard of service. We are the most reliable choice as a partner in semiconductor manufacturing.

And again with the vision/mission statement on the TSMC website today:

Our vision is to be the most advanced and largest technology and foundry services provider to fabless companies and IDMs, and in partnership with them, to forge a powerful competitive force in the semiconductor industry. Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come.

Also according to the current website TSMC has:

  • Served more than 600 customers
  • Manufacturing more than 11,000 products
  • A total managed capacity of 16.4 million eight-inch equivalent wafers in 2013
  • Compiled the largest portfolio of process-proven libraries, IPs, design tools and reference flows
  • Fab 2, 3, 5, 8 and 12 located in the Hsinchu Science Park
  • Fab 6 and 14 located in the Tainan Science Park
  • Fab 15 located in Central Taiwan Science Park
  • A wholly-owned subsidiary, WaferTech in the United States; TSMC China; and its joint venture fab SSMC in Singapore.
  • A US $70,481 million market capitalization as of 7/31/2012
  • 2011 total sales revenue reached a new high at US $14.5 billion
  • Expected 2012 capital expenditure total of US $8.5 billion
  • Listings on the Taiwan and New York Stock Exchanges (TSM)

While the original intention of TSMC was to aid the Taiwanese semiconductor design houses, Dr. Morris Chang clearly had much larger aspirations which transformed the global semiconductor industry into what is today a $300B+ business that is mission critical to modern life.

A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs


ARM and TSMC Beat Revenue Expectations Signaling Strength in a Weakening Economy?

ARM and TSMC Beat Revenue Expectations Signaling Strength in a Weakening Economy?
by Daniel Nenni on 07-25-2012 at 11:00 am

Fabless semiconductor ecosystem bellwethers, TSMC and ARM, buck the trend reporting solid second quarters. Following “TSMC Reports Second Highest Quarterly Profit“, the British ARM Holdings “Outperforms Industry to Beat Forecasts“. Clearly the tabloid press death of the fabless ecosystem claims are greatly exaggerated.

“ARM’s royalty revenues continued to outperform the overall semiconductor industry as our customers gained market share within existing markets and launched products which are taking ARM technology into new markets. This quarter we have seen multiple market leaders announce exciting new products including computers and servers from Dell and Microsoft, and embedded applications from Freescale and Toshiba. In addition, ARM and TSMC announced a partnership to optimize next generation ARM processors and physical IP and TSMC’s FinFET process technology.” Warren East, ARM CEO.

  • ARM’s Q2 revenues were up 12% on Q1 at £135m with profit up 23% at £66.5m.
  • H1 revenues were up 12% on H1 2011 at £268m, with profit up 22% at £128m.
  • 23 processor licenses signed across key target markets from microcontrollers to mobile computing
  • Two billion chips were shipped into a wide range of applications, up 9% year-on-year compared with industry shipments being down 4%
  • Processor royalties grew 14% year-on-year compared with a decline in industry revenues of 7%
  • 3 Mali graphics processor licensess were signed in Q2, of which two were with new customers for Mali technology
  • 5 physical IP Processor Optimisation Packs were licensed.

ARM enters the second half of 2012 with a record order backlog and a robust opportunity pipeline. Relevant data for the second quarter, being the shipment period for ARM’s Q3 royalties, points to a small sequential increase in industry revenues. Q4 royalties are harder to predict as macroeconomic uncertainty may impact consumer confidence, and some analysts have become less confident in the semiconductor industry outlook in the second half. However, building on our strong performance in the first half, we expect overall Group dollar revenues for full year 2012 to be in line with market expectations.

Even more interesting is the recently announced TSMC / ARM multi-year agreement that extends beyond 20 nm technology (16nm) to enable the production of next-gen ARMv8 processors that use FinFETtransistors and leverages ARM’s Physical IP that currently covers a production process range from 250 nm to 20 nm.

“By working closely with TSMC, we are able to leverage TSMC’s ability to quickly ramp volume production of highly integrated SoCs in advanced silicon process technology,” said Simon Segars, executive vice president and general manager, processor and physical IP divisions, ARM. “The ongoing deep collaboration with TSMC provides customers earlier access to FinFET technology to bring high-performance, power-efficient products to market.”

“This collaboration brings two industry leaders together earlier than ever before to optimize our FinFET process with ARM’s 64-bit processors and physical IP,” said Cliff Hou, vice president, TSMC Research & Development. “We can successfully achieve targets for high speed, low voltage and low leakage, thereby satisfying the requirements of our mutual customers and meeting their time-to-market goals.”

This agreement makes complete sense with 90% of ARM silicon going through TSMC and the PR battle Intel is now waging against both ARM and TSMC. But lets not forget the Intel Atom / TSMC agreement of March 2009:

We believe this effort will make it easier for customers with significant design expertise to take advantage of benefits of the Intel Architecture in a manner that allows them to customize the implementation precisely to their needs,” said Paul Otellini, Intel president and CEO. “The combination of the compelling benefits of our Atom processor combined with the experience and technology of TSMC is another step in our long-term strategic relationship.”

Sorry Paul, clearly this was not the case. TSMC is customer driven and Atom had no customers. So there you have it. The agreement was “put on hold” less than a year later:

Intel spokesperson Bill Kircos said no TSMC-manufactured Atoms are on the immediate horizon, though he added that the companies have achieved several hardware and software milestones and said they would continue to work together. “It’s been difficult to find the sweet spot of product, engineering, IP and customer demand to go into production,” the Kircos said.


Given that wrong turn, the current Intel strategy is to offer ASIC services versus the traditional foundry COT (customer owned tooling) for Atom SoCs using a CPU centric 22nm process. This turnkey ASIC service is currently called Intel Foundry Services to which we have heard plenty but have yet to see any silicon. Just my observation of course.


Morris Chang Comments on Q2 2012: 28nm, 20nm, 16nm, FinFets, CAPEX, etc…

Morris Chang Comments on Q2 2012: 28nm, 20nm, 16nm, FinFets, CAPEX, etc…
by Daniel Nenni on 07-19-2012 at 5:42 pm

Twenty eight nanometer is progressing very well. Our output and our yields are both above the plans that we set for ourselves and the plans that we communicated to our customers early in the year. Early in the year means January-February of the year, we set our plans in output and in yields and we, of course, ever since then we tried to exceed the plan and we had also communicated the plan to our customers at the time. And we have indeed exceeded the planned in both output and yields.

We expect to ramp up to about 68,000 wafers per month by the end of the year, 28 nanometer, 68,000 12-inch wafers per month by the end of the year. And by fourth quarter, we will be nearly caught up with the demand and we expect to fully meet the demand from the first quarter of 2013 on we will fully meet the 28 nanometer demand. It is also then that we expect that the 28 nanometer gross margin will catch up with the corporate average.

As I said today, both the defect density and use are better than 40 nanometer at the same stage of the volume ramp and they are also better than what we have – what we planned early in the year and what we communicated to our customers at that time.

Now, next a few words on 20 nanometer, 20 SoC. We have made very good progress on the 112 megabit SRAM yield. Now there are still challenges to overcome in meeting our yield plan of the entire chip. We have made very good progress on 112 megabit SRAM, there are still challenges to overcome in meeting our yield plan of the entire chip, which has both the logic and the SRAM on that, of course.

Now, our 20 nanometer SoC, we believe, is fully competitive with industry leaders, other companies’ 22 nanometer for the served available markets that we serve. For our markets, we believe our 20 SoC is fully competitive with anyone’s 20 nanometer or 22 nanometer offering.And, one important point to make is that our 20 nanometer has the industry’s leading metal pitch of 64 nanometers. Our leading competitors have 80 nanometer metal pitch. That allows an advantage in the device’s density and die size.

Now, as for the timing, we expect our 20 nanometer technology to be qualified by the end of this year and will be ready to support customers (inaudible) in Q1 of 2013. I think that we’ll start some production of 20-nanometer next year, but the small scale, very, very low, what we would call risk type of production basically, but 2014 will be a ramp year for 20-SoC.

Now today, last time I mentioned that we will have a FinFET product after 20 SoC. And today, I’m glad to say that we have been planning the 16 nanometer FinFET. Right after our 20 nanometer (inaudible), which is the 20 SoC, we will offer FinFET at 16 nanometer for significant active power reduction. We expect to achieve speed and density, speed and logic density levels comparable to industry’s leading players 14 nanometer FinFET.

So, we expect our 20 SoC to be competitive with competitors’ 22 nanometer or 20 nanometer products and we expect our 16 nanometer FinFET to be competitive with our competitors’ 14 nanometer FinFET products. You might ask why are we calling it 16. The only reason, in fact, until two days ago, we were undecided on whether to call it 14 or 16 FinFET. Now the only reason we decided to call it 16 FinFET is first, we want to be somewhat modest; second, we are told quite a few major customers ask the 16 FinFET, that designation and we didn’t want to confuse our customers by now switching to 14. But we expect it to be competitive with other people’s 14 nanometer offerings.

Now 16 nanometer FinFET, our 16 nanometer FinFET, is expected to deliver about 25% speed gain given the same standby power over the 20 nanometer SoC. It is expected to give 25% to 30% power reduction at the same speed and the same standby power, and for mobile products, it is expected to give 10% to 20% speed gain at the same total power. As for timing, we expect it to be about one year after 20 SoC namely it should be ready for risk production at the end of 2013 or early 2014, about one year later than the 20 SoC.

Now, why are we having such high capital intensity? Now, well, I think this is actually a focus point of our internal discussion among our top level managers for the last two years now. And basically, we invest in capacity to get future growth. So you look back at history. If you look at our TSMC’s history, during ‘97 and ‘02, between 1997 and 2002, during that six-year period, TSMC’s capital intensity ratio stayed mostly above 60%, 60% during that six-year period. And then was, as you recall, there was a high-tech bubble bursting in late 2000 and early 2001. But in spite of that, our revenue CAGR between ‘97 and ‘07, here after having spending a lot of capital, having sustained high capital intensity for six years, ‘97 to ‘02, our revenue CAGR between ‘97 and ‘07, that’s a 10-year period, was 20%, compounded annual growth rate of 20% in revenue during the 10-year period; the first six of which was marked by high capital intensity. During that 1997 to 2007 period, foundry industry growth was 16% in the same period and ours was 20%. As a result, our market share rose from – foundry market share – from 31% in ‘97 to 43% in ‘07.

And as far as this year’s CapEx is concerned at this point, we are still following the guidance that we gave you last time; I believe NT$8 million to NT$8.5 million. At this point we are still following that. But next year, I am – we are not going to forecast until early next year. But I think I have already given you a view of our reasoning and our strategy and our objectives. So but as to the exact number, I will not give you until early next year.

13 page transcript is HERE.


TSMC Reports Second Highest Quarterly Profit!

TSMC Reports Second Highest Quarterly Profit!
by Daniel Nenni on 07-19-2012 at 5:23 am

We all knew this quarter would be big but maybe not this big. Not all good news though so keep on reading. The news coverage is all over the map, mostly because they have no idea what a pure-play foundry really is. They also underestimate the power of mobile computing which should be a “Revenue by Application” market segment itself. I can’t wait to read what the tabloid analysts/journalists have to say about the results.

Yes, I’m still in Taiwan thus the early morning post. Tomorrow I go to Taipei for some hard earned rest and relaxation. I’m a big fan of trying new things but I just could not bring myself to eat this cricket. The person who did eat it said, “Not as good as I expected.” So there you have it. The fish I did eat and it was very good. I lost the staring match though, that fish did not blink ever. Squid on a stick? No thank you. Double click to enlarge at your own risk.



“The world’s biggest contract chipmaker, and rivals including Samsung Electronics and AMD, could face a downturn in global technology spending as Europe’s woes continue to dent demand and China’s economy slows.” Reuters


AMD is TSMC’s customer not rival and Samsung’s $390M 2011 foundry revenue does not rival TSMC’s $14.5B. Intel and Samsung are rivals, Intel and AMD are rivals, Xilinx and Altera are rivals, etc… I can’t wait to read John’s Cooley’s expert analysis. That should be a hoot. Last time John was in a fab was never. Here is the call transcript, good luck John!

“It makes complete sense to dedicate a whole fab, or two whole fabs, in fact, to just one customer,” Morris Chang said today. He didn’t name any clients it may offer a whole factory to or say whether it has immediate plans to do so. Bloomberg Businessweek.

I will give you three guesses who that customer is and they had all better be fruit.

While all this looks good I do see that some clarification is required:

  • Q4 2011 28nm revenue was 2%
  • Q1 2012 28nm revenue was 5%
  • Q2 2012 28nm revenue was 7%
  • Q3 28nm revenue is forecast to be 14%

That is a very interesting process ramp. Stay tuned, I will ask around a bit before I leave Taiwan. Post your guesses in the comment section or email it to me privately. I’m sure this will turn into great tabloid fodder.

Second-quarter net income rose to NT$41.8 billion, missing the NT$42.2 billion average of 19 analyst estimates compiled by Bloomberg. The earnings result included a NT$2.68 billion charge for its 5.6 percent stake in Shanghai-based SMIC. Consolidated revenue, reported earlier, rose 16 percent from a year earlier to NT$128.1 billion, beating the NT$127.2 billion average of analyst estimates and surpassing the company’s own forecast of NT$126 billion to NT$128 billion.

Looking forward:

Revenue in the three months ending Sept. 30 may be NT$136 billion ($4.5 billion) to NT$138 billion, the Hsinchu, Taiwan- based company said today, compared with the NT$134.8 billion average of 22 analyst estimates compiled by Bloomberg. Second- quarter operating income rose 23 percent to NT$46.7 billion, beating the NT$45 billion average of 15 estimates.

Other reported news is that fabless inventory levels have been increasing due to a decreasing global economy, which would lead to an inventory correction in the fourth quarter and a dip in TSMC’s revenue, which could continue into the first quarter of 2013. Don’t believe a word of it. It is going to be a very merry mobile Christmas! An iPhone5 and iPad Mini for all! Ho ho ho…


How has 20nm Changed the Semiconductor Ecosystem?

How has 20nm Changed the Semiconductor Ecosystem?
by Daniel Nenni on 07-15-2012 at 7:30 pm


What does mango beer have to do with semiconductor design and manufacturing? At a table of beer drinkers from around the world I would have never thought fruity beer would pass a taste test, not even close. As it turns out, the mango beer is very good! Same goes for 20nm planar devices. “Will not work”, “Will not yield”, “Will not scale”, as it turns out 20nm is very good!!! The leading edge fabless people who were scratching their heads six months ago are now scheduling 20nm tape-outs for Q1 2013. Crowd sourcing wins again!

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

I agree with this statement 100%. It comes from a Cadence white paper A Call to Action: How 20nm Will Change IC Design. 20nm was definitely a turning point for the semiconductor ecosystem. Now that the technical wrinkles have been ironed out let’s look at how the fabless business model has evolved.

“There is no doubt we are at a crossroads at the most advanced process technology nodes. In order to take positive steps forward, significant monetary and collaborative investments and resources are required from both the manufacturing and design sides of the equation,” said Ana Hunter, vice president of Samsung’s North American foundry services.

I spoke with Ana before I left for Taiwan. We are in agreement: The industry is at an inflection point and the business model is changing. A simulated IDM environment is required for fabless semiconductor companies to be competitive at the advanced process nodes, absolutely. Check out the new Samsung “Best of Both Worlds: IDM and Pure-Play Foundry” brochure.

Before, during, and after DAC 2012 I asked various engineers from the top fabless semiconductor companies what has changed for them in regards to how they work with the foundries on new process technologies. I also asked the foundries. The IDM-like answers did not surprise me since working with EDA and IP companies on new process nodes is what I do during the day. It may however surprise others who are on the sidelines and believe the latest Intel PR nonsense.

UMC actually pioneered this simulated IDM environment with Xilinx from .25 micron to 40nm. Xilinx employees literally consumed an entire floor of UMC HQ for more than a decade and acted as the dutiful wife delivering many new processes. After the Xilinx 40nm divorce, UMC is no longer monogamous and now has multiple process development mistresses including TI, Qualcomm, and IBM.

TSMC took a different approach which many people overlook. The early days of collaboration started with Reference Flow 1.0 which is now version 12.0 with many new sub flows to be rolled out at TSMC OIP in October. This collaboration included both established and emerging semiconductor and EDA companies. Next came the IP effort with TSMC developing physical IP for reference and production at zero cost to customers. Commercial IP was next with the TSMC “silicon proven” program. IP companies big and small completed an exhaustive qualification program to make it into the TSMC IP catalog. Next came the TSMC “Early Access Program” where a select group of customers and partners were included in process development activities. Correct me if I’m wrong but I believe this started at 90nm. The qualification process for Early Access was also daunting but clearly it was critical to the evolution of the fabless semiconductor ecosystem. The result being the TSMC DTP (Design Technology Platform) Division which employs hundreds of people and has spent hundreds of millions of dollars (my guess) building the industry leading “Simulated IDM platform” you see today!

That brings us to 40nm. At 28nm and even more so at 20nm the fabless people have taken up residence in Hsinchu and the foundry people have “Early Access” to the top fabless companies. Bottom line: you will be hard pressed to differentiate between a Qualcomm, Broadcom, Nvidia, or Xilinx and a modern day IDM, except of course for the actual ownership of the manufacturing equipment. And lets not forget, the now fabless TI, AMD, Fujitsu, LSI Logic and others used to be IDMs, right?

Thank you again UMC and TSMC for leading the way!


Intel Opens a New Front with ASML

Intel Opens a New Front with ASML
by Ed McKernan on 07-10-2012 at 4:00 pm

Behind great humor often lies irony. In the midst of a struggle by the European Union to extract $1.3B from Intel in an ages old Anti-Trust case, the latter makes a strategic move to embolden the Dutch firm ASML to accelerate the development of 450mm and EUV and thus save a continental jewel. What now say EU? When disfunction and bankruptcy abound, beware the need of sovereigns to extract not pints but gallons of blood. Intel sees an end game at hand, not today but in just a couple of years and it plays into its plans to win all of mobile: including Apple and Samsung. They parry the EU assault with a massive $4B investment and prepare to watch the poker players ante up or fold.

Intel Always Fights a Multi-front war knowing that it eventually wears down the enemy. Please, please we don’t speak of enemies unless we are in the realm of politics! However, one should be aware that without TSMC there is no Qualcomm, nVidia, AMD, Broadcom, Marvell and the rest of the ARM camp (especially ARM). And what of Apple and Samsung, the two leaders of the mobile Tsunami who will have 80%+ of the Smartphone and Tablet market by the New Year? They will have a choice to make in which the first one who blinks will have the opportunity to be years ahead of the other.

It is simple mathematics. Assume, conservatively that Intel is two years ahead of TSMC. Now presume Intel, conservatively launches 450mm two years ahead of TSMC, then it is like a 4 year lead in process technology. Now input your die sizes and run the cost models. It is daunting having to stare up at the Matterhorn before the climb begins.

We have learned in the past 6 months that Smartphones and Tablets are demanding leading edge process technology (Qualcomm sold out this year on 28nm 4G LTE chips). This was the one doubt that I had as to whether Qualcomm, nvidia and the rest of the ARM camp were safe in the foundries at an n-1 node while Intel played catch up with a true low power processor and baseband functionality. Intel can now force the game forward and even Apple will now have to consider how wise it is to hang back in older processes. Some amount of their processors will need to step up to the leading edge for cost and performance reasons.

The news articles from yesterday stated that ASML was open to additional investments from other foundries (i.e. TSMC and Samsung). I can see Samsung stepping up. TSMC is an extension of Qualcomm, Broadcom, nVidia and others. They will likely have to devise new long-term agreements from their partners that requires them to pony up dollars for the ASML investment. Or alternatively does Qualcomm write a check to ASML?Does Apple?

The maneuvers lately point to every survivor going vertical, however now we are looking at two separate vertical models. There is the device vertical model with LCD screens, NAND Flash, enclosures etc.. that Apple and Samsung are very adept at. In last weeks blog I mentioned how Intel was funding Taiwanese panel makers to guarantee supply for ultrabook manufacturers (likely at the expense of AMD and nVidia). Now we have Intel letting the world know that being a MAN in the semiconductor industry requires owning more than just fabs. Real Men must now invest in the semiconductor R&D tool chain. The Question that Wall St. should ask is the following: What is the total value that will derive 4-5 years down the line from an investment in ASML’s R&D?

FULL DISCLOSURE: I am Long AAPL, INTC, QCOM, ALTR


Intel’s finfets too complex and difficult?

Intel’s finfets too complex and difficult?
by Tom Dillinger on 07-07-2012 at 7:00 pm

Thanks to SemiWiki readers for the feedback and comments on the previous “Introduction to FinFET Technology” posts – very much appreciated! The next installment on FinFET modeling will be uploaded soon.

In the interim, Dan forwarded the following link to me “ Intel’s FinFETs too complicated and difficult, says Asenov, which provides some (preliminary) analysis on FinFET behavior, from recently published TEM pictures of Intel’s Ivy Bridge designs:
Continue reading “Intel’s finfets too complex and difficult?”


Dragon Boats and TSMC 20nm Update!

Dragon Boats and TSMC 20nm Update!
by Daniel Nenni on 07-01-2012 at 6:30 pm


My luck continues as I missed last week’s typhoon. Fortunately it did not disrupt the annual Dragon Boat Festival. More than just a Chinese tradition, dragon boat racing is an international sports event with teams from around the world coming to Taiwan every year. It is very exciting with the colorful dragon boats and the wild beating of the drums to spur the rowers on. It is an early version of crew (rowing), which is one of the oldest Olympic sports I’m told.

Even more exciting, TSMC has 20nm up on the TSMC website now! Exciting for me at least! This is really cool stuff and it is right around the corner. I also like the new TSMC website and banner ads. It really does show a much more progressive communication style for a foundry.

TSMC provides the broadest range of technologies and services in the Dedicated IC Foundry segment. In addition to general-purpose logic process technology, TSMC’s More-Than-Moore technologies support customers’ wide-ranging needs for devices that integrate specialty features with CMOS logic ICs. TSMC’s More-Than-Moore technologes offer the segment’s richest technology mix, and unmatched manufacturing excellence. Through TSMC Open Innovation Platform™, we provide a robust portfolio of time-to-volume foundry and design services, including front-end design, mask and prototyping services, backend packaging and test services, and front to back-logistics, to speed up More-Than-Moore innovations.


Applications driving 20nm anytime, anywhere, any device

20nm technology is under development to provide best speed/power value for both performance driven products like CPU (Central Processing Unit), GPU (Graphics Processing Unit), APU (Accelerated Processing Unit), FPGA (Field-Programmable Gate Array) and mobile computing applications including smartphones, tablets and high-end SoC (System-on-a-Chip).

In regards to the constant 20nm scaling questions, TSMC 20nm is said to offer a 30%+ performance gain and 25%+ power savings versus 28nm. Has anybody heard what other foundries are claiming lately? It will be interesting to see what the fabless companies can do with 20nm silicon. The success of 28nm will certainly be hard to beat but I can tell you one thing, the fabless guys are spending a lot of time in Hschinsu, EDA and IP vendors are camping out there as well. You will be hard pressed to tell the difference between the old guard IDMs and the leading edge fabless company’s process technology groups, except of course their CAPEX! Expect 20nm risk production to start in Q4 2013, two years to the quarter after 28nm.



TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s managed capacity in 2011 totaled 13.22 million (8-inch equivalent) wafers and is the first foundry to provide 28nm production capabilities.


TSMC’s mission is to be the trusted technology and capacity provider for the global logic IC industry for years to come.

Notice it says “capacity” now. Company mission statements are also reminders for employees so you can bet capacity will be on everyone’s mind for process nodes to come, believe it.




TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work together in several ways. TSMC uses Lorentz’s PeakView for designing their RF IP. In addition to working to support mutual customers, there is collaboration on RDK’s and ongoing correlation projects. These projects ensure accurate results on a wide range of structures and devices. Special focus on capacitor structures, and proper handling of metal fills, guard rings, and pattern ground shields yields excellent correlation up through millimeter wavelength frequencies.

Lorentz says that PeakView is suitable for both design use and sign-off, avoiding the “two-tool” solution that many customers live with.

For design PeakView fits in the flow for new device creation with its PCircuit synthesis. Complex devices can be ‘what-if’ed to arrive at optimal tcoil, transformer, balun, tline and cap configurations that best suit the designer’s needs. Multiple devices can be compared side by side in the Device Editor.

Lorentz emphasized that synthesis with PCircuits does not require costly and time consuming EDA vendor set up: no scalable models are needed. As soon as a new layer stack-up is created in PeakView, the full power of PCircuits is available. They say that new and complex devices with high port counts are easily synthesized. There is no dependency on pre-characterization of the process or the cell. Apparently this opens a much larger design space for customers.

PeakView has a new circuit level capacities to electromagnetically model critical interconnections for RC and especially L in the LPE/PEX flow. Complex critical nets are easily and properly analyzed during design iterations, without manual intervention. Simon said the resulting circuit simulation accuracy improves silicon predictability.

PeakView is now also tightly linked to Laker, as well as to Virtuoso. PeakView’s PCircuits, used to create passive device designs, work equally well in both layout editors. PCircuits are process independent and can easily be created to handle new devices. Unlike Pcells, they are compact, object oriented and PDK driven.

Complex hand drawn or PCircuit generated structures can be electromagnetically simulated by PeakView with its fast full wave 3D field solver. Simon added that PeakView allows for accurate and efficient analysis of metal fills, via arrays and other complex structures.

After electromagnetic simulation, compact convergent DC accurate Physics Based Models (PBM) are generated as RLC sub-circuits, in addition to s-parameter output. Process variation and temperature coefficients are supported.

PeakView has built in visualization for viewing voltage, current and meshing. It also features a built in chart window. Its GUI based operation is perfect for increased designer and modeling team productivity.

Bottom line: Lorentz has built a platform for designers and modeling teams that increases creativity and productivity by letting designers create their own geometry and models, and at the same time improving the efficiency of the EM experts with a faster highly accurate solution for sign off model creation. Lorentz’s new capabilities at the circuit level add significant accuracy to high speed analog design.


TSMC Threater Presentation: Solido Design Automation!

TSMC Threater Presentation: Solido Design Automation!
by Daniel Nenni on 06-17-2012 at 9:00 pm

For a small company, Solido has some very large customers and partners, TSMC being on of them. Why? Because of the high yield and memory performance demand on leading edge technologies, that’s why.

Much has been made of and will continue to be said on the march of Moore’s Law. While economics of scale and performance vs. power are the main justifications, there are increased design challenges that make designs of prior decades seem quaint by comparison. Smaller transistors allow for lower cost per function and more power efficiency, but they also come with increased variation effects, making performance vs. power vs. yield tradeoffs a necessary part of the design flow.

With each successive process shrink, there is a corresponding increase in the number of SPICE simulations required to push design performance while ensuring manufacturability. Solido Design Automation provides solutions for reducing the number of simulations needed during design and verification, while still providing the same or more visibility into design choices, impacts on yield and risk. As a leading provider of efficient variation analysis tools, Solido continues to collaborate with TSMC to deliver effective analysis capabilities on the latest nanometer technologies, supporting designers of memory, standard cell, low power, and analog/RF circuits.

Memory designers have perhaps the greatest challenge in maximizing their design performance within the capabilities of a particular process technology, needing to validate yield and performance to 4-6 sigma on bit cells and sense amps and 2-4 sigma at the array level. While Monte Carlo is the preferred solution, it’s simply impractical to simulate the billions of points needed for 6-sigma analysis. Since the analysis still has to be done, a number of approaches have evolved that seek to bypass Monte Carlo, but they each suffer limitations in accuracy, scalability and, especially, verifiability.

Solido’s Memory+ Suite goes back to the core Monte Carlo analysis designers trust and handles the billions of samples with intelligent adaptive techniques to focus simulation resources towards the high-sigma tails of the distribution. Since Memory+ uses actual Monte Carlo samples, it is able to provide simulation results around the target sigma, high-sigma corners for use in design development and even the full PDF. These options give designers the detailed insights they need into non-linear effects, design sensitivities to make informed sizing decisions.

Unlike other approaches, Solido’s Memory+ is able to handle the more severe non-linear responses, rendering it applicable to a broad range of memory cells. In the following example, a 3- or 4-sigma analysis would appear linear with extrapolation completely missing the failure regions occurring at +/- 4.5-sigma.

Additionally, with the full PDF available for both the bit cell and sense amp, Memory+ can provide 3-sigma analysis at the system level, allowing designers to explore performance vs. yield tradeoffs directly. The following table shows the results of a 3-sigma analysis on a 256Mb SRAM array using the Memory+ System Memory tool, enabling visibility into the tradeoff between timing and system-level yield, in a matter of minutes. The tool is also applicable to system-level DRAM analysis.

Using memory design as just one example, Solido is able to provide designers with the necessary tools to analyze yield and performance, faster and with more consistent quality than before. As shown with Memory+, memory designers can quickly analyze designs at the cell level to 6-sigma and the system-level to 3-sigma, while keeping Monte Carlo and SPICE level accuracy.