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Intel 22nm SoC Process Exposed!

Intel 22nm SoC Process Exposed!
by Daniel Nenni on 12-27-2012 at 9:00 pm
Categories: Foundries, Intel Foundry, TSMC

The biggest surprise embedded in the Intel 22nm SoC disclosure is that they still do NOT use Double Patterning which is a big fat hairy deal if you are serious about the SoC foundry business. The other NOT so surprising thing I noticed in reviewing the blogosphere response is that the industry term FinFET was dominant while the Intel invented term Tri-Gate was rarely used.

The transistor pitch – essentially the distance between two transistors – in the 22nm tri-gate technology is 80nm, which is the smallest pitch that can be produced using single-pattern lithography, Bohr says. “The next generation, 14,” he said, “we’re going to have to convert to Double Patterning to get tighter pitches.”

Mark Bohr is the infamous Intel Senior Fellow who mistakenly predicted the doom of the fabless semiconductor ecosystem. Mark is a funny guy. I remember him putting up an incomplete 22nm defect density trend slide at this year’s Intel Developers Forum and saying “Was it a mistake that I left the numbers out? Yes! Oh my goodness, how could I have done that? But, gee, time is up, so … ”

TSMC on the other hand presents their process defect density numbers every year at the TSMC Tech Symposium. Transparency equals trust in the foundry business, believe it.Back to Double Patterning, I will defer to the experts at Mentor for a complete description. Please see the Double Patterning Exposed articles for technical detail. No registration is required, just click on over.

So the question is: Why does TSMC use the extra lithography steps of Double Patterning for 20nm and Intel does not for 22nm? The answer is Restrictive Design Rules which essentially eliminates any variability in orientation of shapes on critical layers. Intel is very comfortable with incredibly restrictive design rules since they are a microprocessor manufacturer and not a pure-play foundry. Intel can micromanage every aspect of design and manufacturing down to the electron. TSMC on the other hand needs to accommodate different design requirements and intellectual property from 615 customers.In addition to more flexible metal routing, Double Patterning also enables a tighter metal pitch which will put TSMC 16nm head-to-head with Intel 14nm even though, as I explained in 16nm FinFET Versus 20nm Planar, 16nm FF leverages 20nm process technology.

It will be interesting to see how Intel tackles the Double Patterning challenge without the support of the mighty fabless semiconductor ecosystem.Which brings me to another trending topic: Is 20nm Planar a full node, half node, or everybody gonna skip node?

I can tell you as a matter of fact that the top semiconductor companies around the world will NOT skip 20nm. 20nm tape-outs are happening now with production silicon late next year. 20nm will require more processing time from GDS to wafer but it will NOT be cost prohibitive for high volume customers. You are probably familiar with the 80/20 rule where 80% of something or other is controlled by 20% of the people, in the semiconductor industry we call it the 90/10 rule where 90% of the of the silicon shipped is by 10% of the companies and you can bet that they will tape out at 20nm. Designing at 20nm planar will also make the transition to 16nm FinFET easier and I can tell you that EVERYONE will be taping out at 16nm FinFET. That’s my story and I’m sticking to it.

My favorite Mark Bhor quote: “We don’t intend to be in the general-purpose foundry business, I don’t think the volumes ever will be huge for Intel”. Exactly! So what is Intel going to do with all that empty fab space?

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IP Scoring Using TSMC DFM Kits

IP Scoring Using TSMC DFM Kits
by Daniel Payne on 12-20-2012 at 11:00 am
Categories: EDA, Foundries, Siemens EDA, TSMC

Design For Manufacturing (DFM) is the art and science of making an IC design yield better in order to receive a higher ROI. Ian Smith, an AE from Mentor in the Calibre group presented a pertinent webinar, IP Scoring Using TSMC DFM Kits. I’ll provide an overview of what I learned at this webinar. Continue reading “IP Scoring Using TSMC DFM Kits”

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Cortex-A9 speed limits and PPA optimization

Cortex-A9 speed limits and PPA optimization
by Don Dingee on 12-19-2012 at 3:01 pm
Categories: Arm, Cadence, EDA, Foundries, TSMC

We know by now that clock speeds aren’t everything when it comes to measuring the goodness of a processor. Performance has direct ties to pipeline and interconnect details, power factors into considerations of usability, and the unspoken terms of yield drive cost.

My curiosity kicked in when I looked at the recent press release from Cadence announcing they had reached 2.2 GHz on a 28nm dual-core ARM Cortex-A9 with Open Silicon. Are we reaching the limits of the Cortex-A9 in terms of clock speed growth? Or are more improvements in power, performance, and area (PPA) in store for the core?

The raw percentages quoted by Cadence in that release sound great: 10% reduction in design area, 33% reduction in clock tree power, 27% reduction in leakage power compared to an unnamed prior design flow. These new figures were achieved with a combination of the latest RTL compiler, RTL-to-GDSII core optimization, and clock concurrent optimization techniques, which are really targeted at 20nm design but are certainly applicable to less aggressive nodes.

We may be pressing the limits on what the Cortex-A9 core can do at 28nm, and there is likely only one more major speed bump to 20nm in store for the Cortex-A9. I went hunting and found several data points.

ST-Ericsson has (had?) a 2.3 GHz version, with rumbles of 2.5 GHz possible, of the dual-core NovaThor L8580 running on an FD-SOI process. It’s questionable if this device or the rest of the forward ST-Ericsson roadmap ever get to market in light of STMicro wanting to pull out of the JV, the continuing saga of Nokia attempts to recover, and the stark reality of US carriers preferring Qualcomm 4G LTE implementations.

TSMC has taped out a 3.1 GHz dual-core Cortex-A9 on their 28HPM process, which from what I can find is the unofficial record for Cortex-A9 clock speed. However, the “typical” conditions which TSMC cites leave out one detail: active cooling is required, which rules out use of a real world part at this speed in phones or tablets. The economics of yield at that speed are unclear, but they can’t be good otherwise we’d be hearing a lot more about this on processor roadmaps.

Along the lines of how much PPA optimization is possible, I went looking for another opinion and found this SoC Realization white paper from Atrenta, which discusses how PPA fits into the picture. The numbers Cadence is quoting suggest that we’re close to closing the optimization gap for the Cortex-A9, because the big-hitters in the flow have been optimized.

By back of the envelope calculations, if state-of-the-art optimization for a Cortex-A9 gives us 2.2 GHz at 28nm, a process bump to 20nm creates headroom to about 3 GHz. Reports have Apple heading to TSMC for 20nm quad-core designs, but reading between the lines of that the same concerns of power consumption and cooling exist – these chips aren’t slated for iPhones. (As I’ve said before, Apple is driving multiple roadmap lines, one on the A6 for phones, one on the A6x for tablets and presumably the long awaited Apple TV thingie, and likely a third ARM-based chip for future MacBooks probably on the 64-bit Cortex-A50 series core.)

The reason I say the Cortex-A9 likely gets only one more speed bump is explained pretty well in this article, projecting what 64-bit does for ARM-based core performance. While a lot of that is estimation, the point which I agree with is most of the energy for further EDA optimization will be put into the Cortex-A50 series. TSMC and ARM both agree that the drive for 16nm FinFET and beyond is focused on 64-bit cores.

A couple immutable rules of my own when it comes to tech:

  • 10 engineers can make anything work, once; optimization is more interesting.
  • Once something is optimized, it’s optimized, and it’s time to design the next thing.

I think we’re reaching that point on the Cortex-A9, and 3 GHz is about the end of the line for what PPA optimization and process bumps will do. With that said, what may happen is instead of going for higher clock speeds, designers drive the Cortex-A9 for lower power and take it to more embedded applications.

Punditry has its risks, like being wrong a lot or being labeled Captain Obvious. I’m thick skinned. What are your thoughts on this topic, agree or disagree?

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TSMC 28nm and 20nm Update Q4 2012

TSMC 28nm and 20nm Update Q4 2012
by Daniel Nenni on 12-16-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC

The big news in Taiwan last week was another increase in TSMC capital expenditures to $9B in 2013. That number could grow however. Last year TSMC CAPEX was set at $6B and ended up at $8.3B due to rapid 28nm capacity expansion and an accelerated 20nm program. 2013 will be all about FinFETs and manufacturing Apple SoCs so $9B may not cover it.

Taiwan weather was very nice last week, for me anyway. Cooler than normal, cool enough for me to wear a suit and tie, which I very rarely do. It is so rare that people joked and took pictures. And thank you to the Hsinchu Royal Hotel for upgrading me to a suite. You never know when you need a second bathroom in your hotel room.

In 2012 TSMC sales will grow a whopping 19%! TSMC revenue for 2013 is expected to grow 15-20% which is a conservative estimate in my opinion. TSMC 28nm will continue to break process node records and the mobile market will continue to drive economic growth. The semiconductor industry should also do well in 2013 with a predicted 5% growth versus a 3% contraction in 2012.

Speaking of 28nm, TSMC made significant progress in both yield and performance this quarter so we will see even more good 28nm die in 2013 and they will be faster. I give 100% credit to the gate-last implementation of HKMG. Interesting to note, TSMC actually started 28nm research using gate-first HKMG but changed to gate-last due to yield and manufacturing issues. Fortunately TSMC has the advantage of high volume production experience using a broad set of applications. Not just CPUs or GPUs, but FPGAs, SoCs, and dozens of other design types from more than one thousand customers.

IBM on the other hand does not have that breadth of fabless semiconductor customer experience so they went with a gate-first approach at 28nm leaving common platform partners GLOBALFOUNDRIES and Samsung way behind the manufacturing yield and performance curve. TSMC owns the 28nm node and that is why they will have another big revenue year in 2013. TSM stock at $20 in 2013! Believe it!

20nm will be a much more interesting node in regards to competition however. After learning the gate-first lesson, IBM is following TSMC with a gate-last HKMG implementation at 20nm. Unfortunately the added difficulty of 20nm double patterning and lithography challenges, which have yet to be solved at a production level, is causing delays. The fabless semiconductor ecosystem is working around the clock on this and I honestly expect a hockey stick 20nm production curve once this has been solved. Crowdsourcing at its finest!

The other big news was the Intel 22nm SoC process announcement at IEDM last week. I was very vocal about Intel not understanding the SoC business when they jumped into the foundry mix last year. This is a big first step but Intel still has a long way to go. I will do a much more detailed analysis in my next blog and you will see what I mean. Let me apologize in advance to the Intel PR people as I take some wind from their over blown sails.

While I enjoy my monthly trips to Taiwan it sure is good to be home. Absence does make the heart grow fonder.

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Apple Will NOT Manufacture SoCs at Intel

Apple Will NOT Manufacture SoCs at Intel
by Daniel Nenni on 12-09-2012 at 5:00 pm
Categories: Foundries, TSMC

The internet is a funny place where rumors are true and truths are rumors. The latest one has Apple using Intel as a foundry. This is fuel for the rivalry between SemiWiki blogger Ed McKernan and me. Ed says Apple will use Intel, I say Apple will use TSMC, we have a very expensive dinner riding on this one.

TSMC falls on possible competition from Intel
Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest made-to-order chip-maker, fell yesterday on reports it may compete with Intel for Apple orders...

Yes, TSM stock took a hit based on a rumor so we have motive (Apple consumes more than 200,000 12-inch wafers per year). The Intel rumors started last year with Intel saying they would “like” to manufacture the Apple A4 and A5 SoCs. Clearly that did not happen nor will it. Moving an SoC amongst foundries is serious business, serious technical and political business.

Samsung and Intel manufacturing processes could not be farther from compatible. I work with Sagantec, the leading process migration company, and can tell you a migration between Intel and Samsung is not technically feasible. It would be a complete re-design. Apple uses Samsung IP. Apple uses commercial EDA tools certified by Samsung. The ROI is not there for Apple to move the Apple Ax SoC between fabs.

Let’s not forget how Apple became a fabless semiconductor company. They first started with Samsung as an ASIC customer. Apple did the initial RTL design and tossed it over the wall to Samsung for IP integration and physical implementation. Apple then acquired P.A. Semi (Palo Alto Semiconductor) for $278M in 2008 which brought serious SoC design experience in-house. Do a quick search on LinkedIn and you will see quite a few PA Semi people are still at Apple. Apple has also made other acquisitions and investments in the fabless semiconductor ecosystem.

Politically it is a problem as well. Apple’s experience with Samsung, where a vendor (Samsung) directly competes with their largest foundry customer (Apple), will definitely change the way we all do business. Qualcomm is in the same boat with Samsung. Samsung was the largest Snapdragon SoCcustomer and now the Samsung Exynos SoC is replacing Snapdragon. I was at ISSCC when Samsung first presented a paper on Exynos and saw the question line queue up quickly with competing SoC engineers from QCOM, BCOM, TI, Apple, etc. Few if any questions were directly answered as is the Samsung way.

For the record, I have no problem with Samsung competing with customers by providing low cost alternatives. It is good for consumers. It is good for the consumer electronics industry. It is good for the semiconductor ecosystem. It will force Apple and Qualcomm to innovate and differentiate at the different pricing levels. I also have no problem with the resulting legal actions as it will force Samsung to innovate and differentiate rather than replicate. It’s all about the customer experience, better products at affordable price points, that is what business is all about.

Back to the Apple “TSMC versus Intel” debate:

Can Intel be successful in the foundry business? Of course they can but it will not happen anytime soon. It took Samsung 10+ years to get to the number 4 spot. Today Intel Foundry uses the ASIC business model like Samsung did in the early days. Customers throw RTL designs over the Intel wall for physical implementation. This helps Intel learn the SoC foundry business and it protects Intel process secrets. Moving forward Intel will have to develop a fabless semiconductor ecosystem (exposing process secrets) and forge EDA and IP partnerships with the likes of ARM.

Intel will also have to avoid the competing with customers conundrum. The Intel UltraBooks are a blatant copy of Macbooks. The Intel Atom will someday compete with ARM and don’t be surprised if Intel comes out with an SoC of their own. Sounds a bit like Samsung right? Deja vu all over again. TSMC on the other hand is a pure play foundry and does not compete with customers.

My bet is: moving forward Apple will use Samsung for 28nm (iPhone 5s) and TSMC for 20nm (iPhone 6). Intel certainly has a shot at 14nm and 10nm but never ever count out TSMC. If you want to bet a lunch on Apple manufacturing at Samsung or Intel for 20nm post it in the comment section. I will cover all lunch bets against TSMC.

Full disclosure: I can eat my weight in sushi!

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How Apple Plans to Leverage Intel’s Foundry

How Apple Plans to Leverage Intel’s Foundry
by Ed McKernan on 12-09-2012 at 4:00 pm
Categories: Arm, Foundries, Intel Foundry, TSMC

Tim Cook’s strategy to disengage from Samsung as a supplier of LCDs, memory and processors while simultaneously creating a worldwide supply chain from the remnants of former leaders like Sharp, Elpida, Toshiba and soon Intel is remarkable in its scope and breadth. By 2014, Apple should have in place a supply chain for 500M iOS devices (iPhones, iPADs, iTVs and iPODs). Add in the near term foundry relationship with TSMC and it spells not just freedom but a true Vertical Operations independent from its number 1 competitor. Add to this the fact that Apple may soon be lower in cost, an inconceivable thought to most observers. How can Apple have lower cost than Samsung? This is the story of 2013-2014 as Tim Cook is attempting to put the last pieces in place to build affordable $200 iPhones and $250 iPAD Minis for the other half of the world that is currently unaddressed today (eg China Mobile and India).

A recent article in digitimes questions whether TSMC will have enough capacity to support Apple’s projected demand of 200MU while also servicing its other major customers like Qualcomm, Broadcom, nVidia and the rest of the leading edge silicon buyers. Will TSMC make the investment to capture all of mobile while Intel sits on three empty 14nm fabs? Not likely, unless Apple and Qualcomm write checks to guarantee the demand. Six months ago Qualcomm started down the path of diversification when demand skyrocketed and TSMC could not turn on a dime to fulfill. Tim Cook knows Jony Ive will continue to pump out great products at a more rapid pace in the coming quarters and try to deny Samsung and Microsoft an opening like in the past during summer lulls when yearly refreshes were still waiting in the wings. All that is holding Apple back is the global supply chain that is larger and lower cost than what Samsung has today.

Many in the press have spent the past 6 months talking about the transition taking place from Samsung to TSMC. They have overlooked how Apple is leveraging its Japan infrastructure to build LCDs, DRAM and NAND Flash at a time when the Yen is about to collapse. From the mid 1980s to today the Yen has appreciated by 300% relative to the dollar. Moore’s Law is a hugely deflationary force that requires a country to offset its Creative Destruction by inflating away its currency. So the US and half the world linked to the Dollar (including China) have prospered while the Japanese economy has contracted during these past 25 years. If the Yen drops dramatically from 80 to 120 or 150, as is necessary to restart their economy, then Apple will have the beginnings to its low cost strategy to outflank Samsung. A robust, high volume processor and baseband chip supply chain is all that remains.

When the Intel earnings call comes in January, I anticipate a number of analysts will demand a full accounting of the projected fab loadings for 22 and 14nm for 2013 and 2014. The timing of recent leaks on Intel and Apple negotiating a Fab deal is not unexpected. On the table are three 14nm Fabs that require no Apple capital investment to satisfy the demand beyond the 200MU that TSMC and Samsung can supply. Quite likely Apple has the opportunity to support more than 500MU additional units with Intel at current die sizes. But wait, Apple will get an extra shrink and significantly lower power in a move to Intel’s 14nm process. Therefore the Intel Fab option is really the one road available that catapult Apple beyond Samsung in their battle for market share leadership in Smartphones and Tablets. It is also the one option that is unavailable to Samsung.

Analyst Doug Freedman recently speculated that Intel and Apple are considering a Foundry partnership where the former agrees to build ARM chips for the iPhone while the latter will convert the iPAD to x86. It’s possible, but in the end I believe that three empty Fabs running 14nm Finfet is a much stronger religion than x86 architected chips. Intel would be happy with anything Apple wants built because there are tremendous sunk costs in place with the new fabs. This is where TSMC has to be cautious.

While Stacy Smith, Intel’s CFO, repeated at a conference last week that they don’t see PC volume falling again in 2013, there are hints that Ivy Bridge pricing has already been reduced to move the ultrabook price points down to sub $500. Smith also noted that 22nm Fab equipment is now being transitioned into 14nm fabs. The Ireland Fab may be on hold now, but in reality it is like an Aircraft Carrier waiting to be outfitted with Fighters. Six large Fabs are what await the combined x86 and Apple demand. Of the six, less than three are currently needed to support 350M PCs and 20M-x86 based Servers. Any slide in x86 demand just opens up more space for Apple and at lower prices.

At some point the operating margins building the A7 for Apple will cross above those of an Atom chip. Just to be clear, I am saying that an A7 will deliver more profit than an Atom chip when Sales, Marketing and Engineering costs are factored in for the latter. If Intel can sell Apple on its 4G LTE baseband, then the low cost, dual sourced processor and baseband supply chain will be complete.

Scenarios such as those above are only possible when markets are going through huge transitions. I am still intrigued by Intel’s decision to double its fab footprint back in 2010. What were the reasons for the boldness and is that view today still held internally. I can only speculate that they truly believed that they alone would get to 14nm while the rest of the industry faded.

Full Disclosure: I am Long AAPL, INTC, ALTR, QCOM

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Is The Fabless Semiconductor Ecosystem at Risk?

Is The Fabless Semiconductor Ecosystem at Risk?
by Daniel Nenni on 11-18-2012 at 6:00 pm
Categories: Events, Foundries, Intel Foundry, TSMC

Ever since the failed Intel PR stunt where Mark Bohr suggested that the fabless semiconductor ecosystem was collapsing I have been researching and writing about it. The results will be a book co-authored by Paul McLellan. You may have noticed the “Brief History of” blogs on SemiWiki which basically outline the book. If not, start with “A Brief History of Semiconductors”. In finding the strengths of the fabless semiconductor ecosystem I also discovered possible weaknesses.

Deep collaboration with partners and customers is the current mantra we hear at every conference. TSMC even spelled it out at the most recent OIP Forum last month: At 40nm partners and customers started design work when the PDK was release 0.5, at 28nm design work started at PDK 0.1, at 20nm design work started at PDK .05, and 16nm will start at PDK .01. The problem with this is that the earlier the collaboration the more sensitive the data is and this data is being shared with partners and customers who also work with competing foundries. It is a double edged sword and the cause of unnecessary bloodshed in our industry.

The only protection this sensitive data has is the NDA (Non Disclosure Agreement) which ranks right up there with toilet paper in our industry. One of the things I do as a consultant for emerging fabless, EDA and IP companies is help with NDAs. My least favorite is the 3-way NDA where the customer, the EDA vendor, and the foundry all have to sign it. How do you control that information flow?

NDAs have evolved over the years and the recent ones are much more detailed and have some serious legal repercussions but who actually reads them besides me and the lawyers?

The problem is that the EDA industry is very small and we all know each other. Industry people regularly gather at local pubs, coffee houses, and conferences and things tend to slip out. There is also an EDA gossip website that has no respect for sensitive data covered under NDAs.

So you have to ask yourself what is a foundry to do? How do you allow early access to your secret recipes without it being leaked to your competitors? Just some ideas:

Buy an EDA company: I suggested to GLOBALFOUNDRIES in the early days that they tap their oil reserves and buy Cadence. Imagine the seamless tool flow a foundry could create today if they had full control of the tools and information flow. Also imagine the fabless semiconductor industry growth potential if EDA tools were free, like FPGAs, design starts would multiply like bunny rabbits!

Limit the number of EDA companies you do business with:This is my personal nightmare. To cut costs and increase security a foundry would only work closely with the top 2 EDA companies. Granted this would kill emerging EDA companies and stunt the growth and innovation of EDA but it could happen. It would also increase the costs of EDA tools thus killing design starts.

Legal training for all semiconductor ecosystem employees: Use the recent insider trading case law. People are doing serious jail time for leaking Intel, AMD, and Apple financial information. Spend the time to educate your employees on NDAs and focus on controlling the information flow. A couple of hours of prevention could prevent years of incarceration.

If you have other ideas lets discuss it here and I will make sure it is read by the keepers of the secret semiconductor recipes. We have some serious challenges ahead that will require even deeper collaboration so lets be proactive and protect the industry that feeds us.

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TSMC Financial Update Q4 2012!

TSMC Financial Update Q4 2012!
by Daniel Nenni on 11-11-2012 at 4:00 pm
Categories: Foundries, TSMC

The weather in Taiwan last week was very nice, not too hot but certainly not cold. The same could be said for the TSM stock which broke $16 after the October financial report where TSMC reported a sales increase of 15% over September. Revenues for this year thus far increased 19% over last year so why isn’t TSM stock at $20 like I predicted earlier this year?

I blame the Q4 and Q1 Fear, Uncertainty, and Doubt (FUD) everyone is talking about. I blame the “US Fiscal Cliff” everyone is writing about, it even has a wiki page! I was asked by politicians if my family was better off now versus four years ago and the answer is YES, absolutely! Why? Because money is cheap, the interest rate on my debt is less than half, and because I continue to invest in the future.

TSMC has done the same thing. TSMC has spent a record amount this year on CAPEX and R&D and it shows. 28-nanometer revenue and shipments more than doubled during Q3 2012 and total 28nm wafer revenue increased from 7% in Q2 to 13%. Expect 28nm revenue to exceed 20% of total wafer revenue in Q4 and will be more than 10% for the whole year.

TSMC 28nm capacity increased 5% to 3.8 million wafers in Q3 and was fully utilized. As Co-Chief Operating Officer Dr. Shang-Yi Chiang said at ARM TechCon last month, “The biggest 28nm challenge was forecasting with demand for 28nm this year being 2-3x of what was forecast.”

Congratulations to everyone on the success of 28nm TSMC. Teamwork, patience, and investment wins again! Let us not forget the “28nm does not work” FUD at the beginning of the year. As I predicted 28nm will be the best process node we will see for years to come, believe it. Since the other foundries are still struggling with it, I predict 28nm will be the most successful node in the history of TSMC. 28nm may even get a chapter in the book Paul McLellan and I are writing, if not a full chapter, certainly an honorable mention.

Back to the fiscal cliff – what will I do in the next four years? I will continue to invest but also pay down my debt. I did support President Obama for a second term and I strongly suggest he do the same, invest and pay down the National Debt. I offer the same advice to TSMC, continue to invest and the fabless semiconductor ecosystem will have another great four years!

Last quarter TSMC invested $1B in ASML for EUV and 450mm technology. TSMC also bought 35 acres of land in Zuhan (near Hsinchu Science Park) for another GigaFab research and manufacturing facility that will produce 450mm wafers starting at 7nm. TSMC 2013 CAPEX and R&D is expected to be “in the same ball park” as 2012, of course that all depends on 20nm and 16nm FinFETS and how accurate the 2013 forecast is. My guess is that TSMC 2013 revenue will beat 2012 by single digits and, due to the cost of 20nm and 16nm, CAPEX and R&D will also grow by single digits.

Remember, I’m not an analyst, journalist, or financial expert, I’m just a blogger who drives a Porsche.

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ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program

ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program
by Eric Esteve on 11-07-2012 at 12:17 pm
Categories: EDA, Foundries, TSMC

More than one year old now, TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. This soft IP quality program has been the first to be initiated by a Silicon foundry on other than “Hard IP”, and is demonstrating how IP support, whether hard or soft, is important in TSMC strategy to best support their customers and shorten the design to Silicon delay and reduce the TTM. Currently, over 15 soft IP suppliers have been qualified through the program, including ARM, as recently announced by TSMC at ARM TechCon.

How does the flow works? Atrenta’s SpyGlass® platform provides a powerful combination of proven design analysis tools with broad applicability throughout the SoC flow. The SpyGlass platform includes a tool suite for linting, CDC verification, DFT, constraints analysis, routing congestion analysis and power management applicable at RTL as well as the gate level. Providing visibility to design risks early and at high design abstractions, SpyGlass enables Early Design Closure® –During the course of chip development, design goals evolve and get refined from the initial RTL development phase to the final SoC implementation phase. The SpyGlass platform offers a consistent solution that can be used effectively at each stage of the design process to achieve the respective design goals. The use of the right SpyGlass tools at the right stage of design development helps design teams achieve a predictable repeatable methodology.

The list of design goals addressed by GuideWare, a set of pre-packaged methodologies for SpyGlass, show that the risk of failure is early addressed, and can be minimized:

  • Will the design simulate correctly?
  • Are clocks and resets defined correctly?
  • Will the design synthesize correctly? Are there unintended latches or combo loops?
  • Will gate simulations match RTL simulations?
  • What will the test coverage be?
  • What is the power consumption of a given block?
  • What is the profile of this IP? (For example, gates, flops, latches, RAMS/ROMS, I/Os, tristates, clocks)
  • Are there any inherent risks or non-standard design practices used in this IP?
  • Are there any adaptation issues in the target SoC, such as power, routability or congestion?
  • Are all the incoming blocks truly ready for integration? Are they clean in terms of clocks/resets and constraints?
  • What are possible inter-block issues? (For example, are block-level constraints complete and coherent with target SoC constraints?)
  • What are “common-plane” issues among heterogeneous blocks? (For example, scan chain management and test blockages at the SoC level)
  • Can I leverage my block-level work (waivers, constraints) at the SoC level?

Coming back to TSMC soft IP quality assessment program, we can see that the list of IP partners is a who’s who including from Network-on-Chip IP vendor Arteris, DSP IP core supplier CEVA, PCI Express IP core (PLDA), configurable CPU IP core (Tensilica) to GPU and CPU IP core vendors with ARM Ltd. and Imagination Technologies, Video and Display IP (Chips and Media), and scanning also Dolphin Integration, Cosmic Circuits or GlobalUniChip, provider of mixed-signal IP. That’s really make sense that ARM, the #1 IP vendor, join this program, as well as it would really makes sense that at least two of the top 3 EDA & IP vendor, Cadence and Synopsys, would join the program, sooner or later…

Eric Esteve from IPNEST

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16nm FinFET versus 20nm Planar!

16nm FinFET versus 20nm Planar!
by Daniel Nenni on 11-04-2012 at 8:10 pm
Categories: FinFET, Foundries, TSMC

The common theme amongst semiconductor ecosystem conferences this year is FinFETS, probably the most exciting technology we will see this decade. A lot has been written on SemiWiki about FinFETS, it is one of the top trending search terms, but there is some confusion about the process naming so let me attempt to explain.

In planar process technologies the 28nm or 20nm implies the minimum transistor gate length of 28nm or 20nm. Corresponding to that lithographic capability are two other critical dimensions: the “contacted gate pitch” and the “metal pitch” for the lowest, thinnest metal layers. (Higher metal layers will be thicker with less resistance which are more suitable for longer routes but will have a greater width+space design pitch.)

Given that, the 16nm FinFET process technology is a bit of a misnomer. It was probably named by Marketing people to imply that the resulting performance when transitioning from planar to FinFET in a 20nm lithography process would be “between 20nm planar and 14nm FinFET”.

Why 16nm FinFETS you ask? Two reasons: (1) EUV is late so a true 14nm FinFET process will not be possible by 2015 and (2) Customers designing mobile devices were not willing to wait for the power savings FinFETS have to offer. As a result, the current 20nm lithography process was modified for FinFETs, and the 16nm FinFET process was born.

If you were to ask, “What is the minimum gate length, contacted gate pitch and metal pitch for 16nm FF, and how does that differ from 20nm SoC?”, you would get the answer that it’s the same litho design rules, just a different transistor structure.

There is one additional measurement that is introduced in a FinFET technology: the effective device width per micron. These are transistor parameters, and they are an indicator of performance, but they are relatively independent of the contacted gate pitch + metal pitch, which define the achievable circuit density.

The IBM 14nm FinFET tape out briefing provided some interesting process details. Disclosing this type of information is certainly not IBM-like so the stakes are obviously high in the race to FinFETs:

[TABLE] align=”left” style=”width: 470px”
|-
|
| 32nm
| 28nm
| 20nm
| 14nm
|-
| Architecture
| Planar
| Planar
| Planar
| FinFET
|-
| Contacted poly pitch
| 126nm
| 114nm
| 90nm
| 80nm
|-
| Metal pitch
| 100nm
| 90nm
| 64nm
| 64nm
|-
| Local interconnect
| No
| No
| Yes
| Yes
|-
| Self-aligned contact
| No
| No
| No
| No
|-
| Strain engineering
| Yes
| Yes
| Yes
| Yes
|-
| Double patterning
| No
| No
| Yes
| Yes
|-

Bottom line, lithographically, both 16nm and 14nm FinFET processes are still effectively offering a 20nm technology with double-patterning of lower-level metals and no triple or quad patterning.

One team has chosen to define the performance of their FinFET as a “half node” improvement (e.g., 20nm ->16nm), whereas the other has chosen to represent the performance of their FinFET as equivalent to a “full-node shrink” (20nm -> 14nm). There will be slightly different fin_height, fin_thickness, and fin_pitch parameters between the two processes but the circuit density is really still the same as 20nm.

Some designs might be smaller but in general I think FinFets at 16nm and 14nm will offer significantly lower power consumption and leakage but only marginally better performance and area than 20nm planar, just my opinion of course.

Who do you think will be first to get FinFETS into volume production? Would it be TSMC, Samsung, or GF? Check out the SemiWiki FinFET poll HERE. Anybody can vote so please do.

Also see:

GLOBALFOUNDRIES 14nm FAQ

FinFET Wiki