WP_Term Object
(
    [term_id] => 18
    [name] => Intel Foundry
    [slug] => intel
    [term_group] => 0
    [term_taxonomy_id] => 18
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 482
    [filter] => raw
    [cat_ID] => 18
    [category_count] => 482
    [category_description] => 
    [cat_name] => Intel Foundry
    [category_nicename] => intel
    [category_parent] => 158
    [is_post] => 
)
            
intel foundry SemiWiki 800x100 banner
WP_Term Object
(
    [term_id] => 18
    [name] => Intel Foundry
    [slug] => intel
    [term_group] => 0
    [term_taxonomy_id] => 18
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 482
    [filter] => raw
    [cat_ID] => 18
    [category_count] => 482
    [category_description] => 
    [cat_name] => Intel Foundry
    [category_nicename] => intel
    [category_parent] => 158
    [is_post] => 
)

Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First Generation

Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First Generation
by Daniel Nenni on 09-02-2026 at 10:00 am

Intel 18A P Extends Intel 18A with Significant Power and Performance Gains

Intel Foundry has a blog on LinkedIn that is worth a look. The blogs are by trusted Intel Foundry technical experts and are filled with content. I will cherry pick write a bit about them but be sure and subscribe to this, absolutely.

Intel 18A-P is not a new process node in the conventional sense. It is a performance-enhanced derivative… Read More


Intel’s 14A Is Winning the Race Against Defects

Intel’s 14A Is Winning the Race Against Defects
by Daniel Nenni on 08-31-2026 at 2:00 pm

Intel’s 14A Is Winning the Race Against Defects

Intel’s next-generation 14A manufacturing process is showing unusually strong early progress, with defect density falling faster than the company expected. The improvement gives Intel a technical boost as it attempts to restore confidence in its manufacturing operation, win foundry customers and demonstrate that years… Read More


Crescent Island: Turning Memory Capacity into Agentic AI Throughput

Crescent Island: Turning Memory Capacity into Agentic AI Throughput
by Admin on 08-27-2026 at 2:00 pm

Intel Crecesent Island Hot Chips 2026

Intel’s Crescent Island is a discrete data-center GPU designed for agentic AI inference, where performance is constrained by more than matrix arithmetic. Multi-step agents impose latency through repeated model calls and tool interactions, consume large memory capacity for weights and long-context key-value caches, and… Read More


Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon

Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon
by Admin on 08-26-2026 at 2:00 pm

Intel Diamond Rapids Hot Chips 2026

Akhilesh Kumar & Krishnakanth Sistla, Intel

Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional… Read More


Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance

Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance
by Admin on 08-25-2026 at 2:00 pm

Intel Wildcat Hot Chips 2026

Lance Hacking, Intel

Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More


Intel Eyes a Memory Comeback as AI Rewrites Chip Economics

Intel Eyes a Memory Comeback as AI Rewrites Chip Economics
by Daniel Nenni on 08-21-2026 at 6:00 am

Intel Eyes Memory Comeback

Intel is considering a return to memory technology decades after abandoning mainstream DRAM and, more recently, selling its NAND business. Chief executive Lip-Bu Tan has argued that memory should no longer be viewed simply as a low-margin commodity. Artificial intelligence is turning bandwidth, latency and data movement … Read More


The Twelve-Month Rule Does Not Describe a New Fab

The Twelve-Month Rule Does Not Describe a New Fab
by Admin on 08-20-2026 at 10:00 am

capex to wafer starts lag

By Nikhil Shah

Capital spending is often treated as if it becomes semiconductor capacity about twelve months later. That can be a useful rule for equipment installed in an existing fab. It is a poor description of a new fab built from the ground up.

I tested the distinction using five advanced-node projects in the United States where… Read More


Comparing Intel EMIB and Intel Foveros

Comparing Intel EMIB and Intel Foveros
by Daniel Nenni on 08-12-2026 at 10:00 am

Comparing Intel EMIB and Intel Foveros SemiWiki

Intel EMIB and Intel Foveros are advanced semiconductor-packaging technologies designed to combine multiple silicon dies, or chiplets, within one processor package. Both support heterogeneous integration: manufacturers can build different functions using the process technology best suited to each one, then connect … Read More


Intel Foundry and the DAC2026 Ecosystem

Intel Foundry and the DAC2026 Ecosystem
by Daniel Nenni on 08-07-2026 at 6:00 am

Intel Foundry DAC2026

The Design Automation Conference in Long Beach was a pleasant surprise. It drew strong attendance from leading companies across the semiconductor ecosystem, along with an impressive number of newcomers. AI-focused EDA companies came out in force—and delivered.

Intel Foundry also made its presence felt, reminding everyone… Read More


TSMC CoPoS Versus Intel EMIB Semiconductor Packaging

TSMC CoPoS Versus Intel EMIB Semiconductor Packaging
by Daniel Nenni on 07-24-2026 at 10:00 am

TSMC CoPos Versus Intel EMIB 2026

TSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, address the same strategic problem: integrating increasingly large, heterogeneous chiplet systems. However, they attack different physical constraints. CoPoS is an emerging panel-level … Read More