TSMC’s Innovations in Physical Design for Semiconductor Scaling

In a 2017 ISPD presentation, TSMC Fellow LC Lu outlined critical challenges and innovations in physical design to sustain power, speed, and area scaling trends in semiconductors. As Moore’s Law faces economic hurdles, process-design co-optimization emerges as key to extending it. Lu emphasized application-optimized platforms for mobile, high-performance computing (HPC), automotive, and IoT, balancing area, performance, and power (PPA) with functional safety and ultra-low power needs.

Semiconductor trends highlight slowing primary dimension scaling (metal, gate, fin pitches), making area reduction harder. Innovations like fin depopulation boost cell density by reducing fins from 3-4 in 16nm to 2 in 7nm, easing scaling pressure. This not only increases logic density by up to 3x but also enhances speed-power efficiency: higher-fin cells offer peak speed, while fewer fins excel at same-power speed or same-speed low power. Cell utilization rises from 70% to 80%, aided by power plan optimizations.

Power grid (PG) enhancements are pivotal for logic density. To counter IR drop, PG via counts increase across generations, but shrinking pitches harms routing. Evolving from uniform to dual M1 architectures via top-down or bottom-up co-design allows better cell placement freedom. Power stubs over straps maximize cells under PG, and staggered pins add access points (from 5 to 6), minimizing unused space.

Extreme Ultraviolet (EUV) lithography further densifies routing. Compared to inverse lithography or multiple patterning, EUV single patterning and directed self-assembly (DSA) enable finer pitches (12-16nm half-pitch). Shifting metal:poly pitch from 1:1 to 2:3 provides more metal resources, reducing coupling capacitance and boosting routing tracks, though requiring dual library sets for offsets.

Performance scaling grapples with exponential metal/via resistance growth—up to 3x from 40nm to 5nm—dominating delay (50% BEOL impact at 5nm). Via pillars mitigate this: large drivers, thick upper metals, and pillar structures slash transistor, wire, and via resistance. Automated EDA flows insert electromigration (EM) and performance via pillars across placement, CTS, and routing, reducing BEOL delay impact significantly.

Power scaling leverages ultra-low voltage (ULV) for IoT efficiency, but challenges functionality and variation. Solutions include skew/fine-grained cells, high-stack designs, transmission gates, and multi-bit flops to curb delay degradation. Flop robustness demands high-sigma checks for write paths. Delay variation explodes at low VDD, turning non-Gaussian; new models split distributions into early/late for accurate STA, aligning with Monte Carlo simulations via advanced statistical OCV.

Heterogeneous integration via 3D packaging achieves low-cost, high-performance systems. InFO (Integrated Fan-Out) and CoWoS (Chip-on-Wafer-on-Substrate) outperform traditional SIP/MCM, enabling vertical stacking for better form factors and bandwidth. InFO variants (PoP, Multi-chip) suit small dies (<400mm², <1000 I/Os), while CoWoS handles large HPC integrations (>1000mm², >3000 I/Os). Co-design flows incorporate inter-die DRC/LVS, SI/PI simulations, thermal-aware EM/IR, yielding 12% better thermal dissipation and 5-10% voltage droop reduction in InFO-PoP with IPD.

Machine learning (ML) tackles rising physical design complexity. TSMC’s platform extracts features from APR databases, trains models to predict routing congestion and detours, eliminating biases in traditional EDA heuristics. This enables pre-route optimizations, like accurate ARM A72 clock gating, boosting post-route speed by 40-150MHz with 95% detour prediction accuracy.

In conclusion, these innovations—fin depopulation, EUV, via pillars, ULV modeling, 3D integration, and ML—extend Moore’s Law through EDA-physical design synergy. As nodes shrink, such co-optimizations ensure complex 3D SoCs meet PPA demands, driving future mobile, HPC, and IoT advancements.

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