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WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
by Daniel Nenni on 11-28-2023 at 10:00 am

Agnisys Mux Synchronizer

This webinar looks at the challenges a Design Engineer could face, such as when various IP blocks within an SoC are required to work in different clock domains to satisfy the power constraints.

Abstract:
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints.… Read More


Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin

Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin
by Mike Gianfagna on 11-28-2023 at 6:00 am

Siemens Digital Industries Software Collaborates with AWS and ARM To Deliver an Automotive Digital Twin

 

According to McKinsey & Company, a digital twin is a digital representation of a physical object, person, or process, contextualized in a digital version of its environment. Digital twins can help an organization simulate real situations and their outcomes, ultimately allowing it to make better decisions. Anyone… Read More


Synopsys.ai Ups the AI Ante with Copilot

Synopsys.ai Ups the AI Ante with Copilot
by Bernard Murphy on 11-27-2023 at 10:00 am

Synopsys.ai Stack 111623

Last week Synopsys announced their next step in generative AI (GenAI) in Synopsys.ai Copilot based on a collaboration with Microsoft. This integrates Azure OpenAI together with existing Synopsys.ai GenAI capabilities to extend Copilot concepts to the EDA world. For those of you unfamiliar with Copilot, this is a development… Read More


Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
by Kalar Rajendiran on 11-27-2023 at 6:00 am

Synopsys 224G SerDes IP InterOp Multiple Tradeshows

Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous… Read More


Podcast EP195: A Tour of Mythc’s Unique Analog Computing Capabilities with Dave Fick

Podcast EP195: A Tour of Mythc’s Unique Analog Computing Capabilities with Dave Fick
by Daniel Nenni on 11-24-2023 at 10:00 am

Dan is joined by Dave Fick, co-founder and CEO of Mythic. Dave leads Mythic to bring groundbreaking analog computing to the AI inference market. With a PhD in Computer Science & Eng from Michigan, he brings a wealth of knowledge and expertise to the industry.

Dan explores Mythic’s unique analog computing capability … Read More


CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor

CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor
by Daniel Nenni on 11-24-2023 at 6:00 am

MeghaliChopra highres cropped

Dr. Meghali Chopra is co-founder and CEO of SandBox Semiconductor. She is responsible for SandBox’s vision and strategy and oversees the development of SandBox’s software products and technologies. Dr. Chopra received her PhD in Chemical Engineering from the University of Texas at Austin where her research focused … Read More


Generative AI for Silicon Design – Article 4 (Hunt for Bugs)

Generative AI for Silicon Design – Article 4 (Hunt for Bugs)
by Anshul Jain on 11-23-2023 at 8:00 am

Generative AI for Silicon Design 4

In the complex world of silicon design, ensuring the accuracy and reliability of our designs is paramount. As our chips become more sophisticated, the process of bug hunting—identifying and rectifying errors in our designs—becomes even more critical. Generative AI has the potential to revolutionize the silicon design industry… Read More


Handling metastability during Clock Domain Crossing (CDC)

Handling metastability during Clock Domain Crossing (CDC)
by Daniel Payne on 11-22-2023 at 10:00 am

synchronizer min

SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer … Read More


Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model

Predicting Stochastic Defectivity from Intel’s EUV Resist Electron Scattering Model
by Fred Chen on 11-22-2023 at 6:00 am

Predicting Stochastic Defectivity from Intel's EUV Resist Electron Scattering Model

The release and scattering of photoelectrons and secondary electrons in EUV resists has often been glossed over in most studies in EUV lithography, despite being a fundamental factor in the image formation. Fortunately, Intel has provided us with a laboriously simulated electron release and scattering model, using the GEANT4… Read More


Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing

Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
by Kalar Rajendiran on 11-21-2023 at 10:00 am

CEVA Comprehensive Edge AI Portfolio

The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are… Read More