Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
GaN HEMT modeling with ANN parameters targets extensibilityDesigners choosing gallium nitride (GaN) transistors may face…Read More
AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 - China & Delays & CHIPS Act?- AMAT has OK QTR but outlook below…Read More
More Headwinds - CHIPS Act Chop? - Chip Equip Re-Shore? Orders Canceled & Fab Delay- CHIPS Act more likely to be maimed…Read More
AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:
There are lots of places that Apache is going to popping up in the next few weeks.
Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about “Chip-Package-System convergence: bridging multiple disciplings… Read More
SICAS (Semiconductor Industry Capacity Statistics) has released its 2Q 2011 data with significant changes in membership. The data is available through the SIA at: SICASdata The SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or United… Read More
Vertical integration, as I have noted in previous blogs, is the way to domination and maximum profitability. That is unless someone else has beaten you to the punch with an even bettermodel. Apple is now executing a product and manufacturing supplier strategy that will force Samsung to lose lots of money and then ultimately split… Read More
Very interesting question from Zahrein in this thread: “how to manage an embedded USB 3.0 PHY Verification”? To clearly position the problem, Zahrein need to run the RTL verification of a complete SoC integrating an USB 3.0 function, that is the Controller (digital) and the PHY (Analog Mixed Signal) embedded in the SoC. The question,… Read More
EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.
Tomorrow in San Jose you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.
Here are some of the topics that will interest IC designers… Read More
Every SOC that is designed must be tested and the premier conference for test is ITC, held last month in Anaheim, California.
I spoke with Robert Ruiz of Synopsys by phone on September 21st to get an update on what is new with EDA for test engineers this year. Robert and I first met back at Viewlogic when Sunrise was acquired in the 90’s.… Read More
If you follow the SemiWiki Twitter feed you may have noticed that The Motley Fool (Seth Jayson) did three more articles on TSMC financials. The first Foolish article was blogged on SemiWiki as “TSMC Financial Status and OIP Update”.
The next three Fool Hardy articles look at cash flow (the cash moving in and out of a business), accounts… Read More
Don’t forget the SpringSoft Community Conferences next week in Austin on Tuesday and in San Jose on Thursday. There is no charge and you even get a free lunch (see “no such thing as…”).
The morning in Austin is focused on functional closure and how to leverage SpringSoft’s verification technology… Read More
At the TSMC Open Innovation Platform Ecosystem Forum (try saying that three times in a row) next week (on Tuesday 18th), Atrenta will present a paper on the TSMC soft IP qualification flow. It will be presented by Anuj Kumar, senior manager of the customer consulting group.
More and more, chips are not put together what we think of … Read More
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