It is well-known that AI is upending conventional wisdom for system design. Workload-specific processor configurations are growing at an exponential rate. Along with this is an exponential growth in data bandwidth needs, creating an urgency for 1.6T Ethernet. A recent SemiWiki webinar dove into these issues. Synopsys and … Read More





Safeguard power domain compatibility by finding missing level shifters
In the realm of mixed signal design for integrated circuits (ICs), level shifters play a critical role for interfacing circuits that operate at different voltage levels. A level shifter converts signal from one voltage level to another, ensuring compatibility between components. Figure 1 illustrates a missing level shifter… Read More
A Timely Update on Secure-IC
I last wrote about Secure IC back in 2023, a provider of embedded security technologies and services. Cadence announced at the beginning of 2025 their intention to acquire this company, which warrants a check-in again on what they have to offer. Secure-IC addresses multiple markets, from automotive, through defense/space and… Read More
The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2
Prolog – Interface Protocols: Achilles’ Heels in Today’s State-of-the-art SOCs
June 30 was only a week away when Varun had a sleepless night. The call from the datacenter manager the evening before alerted him on a potential problem with the training of a new Generative AI model. Six months earlier Varun’s employer installed… Read More
Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
As RISC-V adoption accelerates across the semiconductor industry, so do the concerns about hardware security vulnerabilities that arise from its open and highly customizable nature. From hardware to firmware and operating systems, every layer of a system-on-chip (SoC) design must be scrutinized for security risks. Unlike… Read More
Metal fill extraction: Breaking the speed-accuracy tradeoff
As semiconductor technology scales and device complexity increases, accurately modeling the parasitic effects of metal fill has become critical for circuit performance, power integrity, and reliability. Metal fill is a crucial part of the manufacturing process, ensuring uniform layer density, improving planarization,… Read More
How Arteris is Revolutionizing SoC Design with Smart NoC IP
Recently, Design & Reuse held its IP-SoC Days event at the Hyatt Regency in Santa Clara. Advanced IP drives a lot of the innovation we are seeing in chip design. This event provides a venue for IP providers to highlight the latest products and services and share a vision of the future. IP consumers are anxious to hear about all the… Read More
CEO Interview with Ido Bukspan of Pliops
Prior to becoming CEO of Pliops in 2023, Ido Bukspan was the senior vice president of the Chip Design Group at NVIDIA and one of the leaders at Mellanox before it was acquired by NVIDIA for nearly $7 billion.
Tell us about your company.
Pliops accelerates and amplifies the performance and scalability of global GenAI infrastructure,… Read More
CEO Interview with Roger Cummings of PEAK:AIO
Roger Cummings is the CEO of PEAK:AIO, a company at the forefront of enabling enterprise organizations to scale, govern, and secure their AI and HPC applications. Under Roger’s leadership, PEAK:AIO has increased its traction and market presence in delivering cutting-edge software-defined data solutions that transform commodity… Read More
Video EP4: A Deeper Look at Advanced Packaging & Multi-Die Design Challenges with Anna Fontanelli
In this episode of the Semiconductor Insiders video series, Dan is once again joined by Anna Fontanelli, founder and CEO of MZ Technologies. In this discussion, more details of the challenges presented by advanced packaging and multi-die design are explored. Anna provides details of what’s involved in architectural … Read More
Intel’s IDM 2.0