Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop EngineeringAt Hot Chips 2026, OpenAI presented Jalapeño, an…Read More
Rethinking Phase Jitter: An Algorithmic Approach to Signal IntegrityByline: Richard Shreiner Modern semiconductor architectures are pushing…Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI ChipsSiemens has announced advances in its collaboration with…Read More
TSMC’s AI Expansion Signals a Broader Shift in ComputingTSMC is describing an artificial intelligence boom that…Read More
Terafab's Single Roof: Why Packaging, Not Lithography, Decides High VolumeBy Shaurya Seth Terafab is one of the…Read More
Recently, I reported on my conversation with Cristian Amitroaie, CEO of AMIQ EDA, about automated generation of documentation from design and verification code. Before we chose that topic for a post, Cristian described several capabilities of the AMIQ EDA product family that might be of interest to design and verification engineers.… Read More
Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance,
Charlie Su, President and CTO of Andes Technology, delivered a compelling keynote at the 2025 RISC-V Summit North America, asserting that RISC-V is primed to drive the burgeoning field of Intelligent General Computing. This emerging paradigm integrates AI and machine learning into everyday computing devices, from AI-enabled… Read More
Quantum algorithms must be simulated on classical computers to validate correct behavior, but this looks very different from classical logic simulation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our… Read More
Earlier this month, TechInsights did a teardown of the Kirin 9030 chip found in Huawei’s Mate 80 Pro Max [1]. Two clear statements were made on the findings: (1) the transistor density of SMIC’s “N+3” process was definitely below that of the earlier 5nm processes from Samsung and TSMC, and (2) metal pitch was aggressively scaled
Daniel is joined by John Maculley, Global High-Tech Industry Strategy Consultant at Dassault Systèmes. John has over 20 years of experience advancing innovation across the semiconductor and electronics sectors. Based in Silicon Valley, he works with leading foundries, OSATs, design houses, and research institutes worldwide… Read More
Taiwan Semiconductor Manufacturing Company (TSMC) is widely regarded as the world’s most trusted semiconductor foundry, a reputation built over decades through technological leadership, business model discipline, operational excellence, and reliability. In an industry where trust is as critical as transistor density,… Read More
In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.
Patterson began with humor, noting… Read More
Generative AI has transformed software development, enabling entire applications to be built in minutes. But despite similar progress in AI-generated RTL, hardware verification remains a major bottleneck. RTL can be produced quickly, yet proving its correctness is extraordinarily difficult. This has revived a long-standing… Read More
Taiwan Semiconductor Manufacturing Company, the world’s leading dedicated semiconductor foundry, has long prioritized customer-centric innovation to maintain its competitive edge in a rapidly evolving industry. TSMC is known as “The Trusted Foundry” for this reason.
Amid increasing complexity in… Read More
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