Eng. Islam Nashaat received his B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2010 and 2017, respectively. He joined Si-Vision as an Analog Physical Design Engineer in 2010, where he initiated the company’s CAD team in 2013, and became CAD and Physical Design Team Lead in 2016 after the company’s flagship … Read More
TSMC N3E is ready for designs, thanks to IP from Synopsys
TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched. Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More
Synopsys Panel Updates on the State of Multi-Die Systems
Synopsys recently hosted a cross-industry panel on the state of multi-die systems which I found interesting not least for its relevance to the rapid acceleration in AI-centric hardware. More on that below. Panelists, all with significant roles in multi-die systems, were Shekhar Kapoor (Senior Director of Product Management,… Read More
Placement and Clocks for HPC
You are probably familiar with the acronym PPA, which stands for Power/Performance/Area. Sometimes it is PPAC, where C is for cost, since there is more to cost than just area. For example, did you know that adding an additional metal layer to a chip dramatically increases the cost, sometimes by millions of dollars? It requires a … Read More
Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge
Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.
While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today,… Read More
Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem
As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently… Read More
Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design
The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs,… Read More
Can Generative AI Recharge Phone Markets?
Consensus on smartphone markets hovers somewhere between slight decline and slight growth indicating lack of obvious drivers for more robust growth. As a business opportunity this unappealing state is somewhat offset by sheer volume ($500B in 2023 according to one source) but we’re already close to peak adoption outside of … Read More
SPIE- EUV & Photomask conference- Anticipating High NA- Mask Size Matters- China
– SPIE EUV & Photomask conference well attended with great talks
– Chip industry focused on next gen High NA EUV & what it impacts
– Do big chips=big masks? Another Actinic tool?
– AI & chip tools, a game changer- China pre-empting more sanctions
The SPIE EUV & Photomask conference in Monterey
… Read MorePodcast EP186: The History and Design Impact of Glass Substrates with Intel’s Dr. Rahul Manepalli
Dan is joined by Dr. Rahul Manepalli. Rahul is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization. Rahul and his team are responsible for developing the next generation of materials, processes and equipment for Intel’s package substrate pathfinding and development… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay