In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More
IEDM 2025 and the 100th Anniversary of the FETThe International Electron Devices Meeting (IEDM) is the…Read More
Intel to Compete with Broadcom and Marvell in the Lucrative ASIC BusinessThe second chapter of our book “Fabless: The…Read More
Why IP Quality and Governance Are Essential in Modern Chip DesignBy Kamal Khan In today’s semiconductor industry, success…Read More
U.S. Electronics Production GrowingU.S. electronics production has been on an accelerating…Read MoreCEO Interview with Faraj Aalaei of Cognichip
Faraj Aalaei is a successful visionary entrepreneur with over 40 years of distinguished experience in communications and networking technologies. As a leading entrepreneur in Silicon Valley, Faraj was responsible for building and leading two semiconductor companies through IPOs as a founder and CEO.
Post acquisition of … Read More
Rethink Scoreboards to Supercharge AI-Era CPUs
By Dr. Thang Minh Tran, CEO/CTO Simplex Micro
Today’s AI accelerators—whether built for massive data centers or low-power edge devices—face a common set of challenges: deep pipelines, complex data dependencies, and the high cost of speculative execution. These same concerns have long been familiar in high-frequency microprocessor… Read More
CEO Interview with Dr. Noah Sturcken of Ferric
Noah Sturcken is a Founder and CEO of Ferric with over 40 patents issued and 15 publications on Integrated Voltage Regulators. Noah leads Ferric with focus on business development, marketing and new technology development. Noah previously worked at AMD R&D Lab where he developed Integrated Voltage Regulator (IVR) technology.… Read More
Jitter: The Overlooked PDN Quality Metric
Bruce Caryl is a Product Specialist with Siemens EDA
The most common way to evaluate a power distribution network is to look at its impedance over the effective frequency range. A lower impedance will produce less noise when transient current is demanded by the IC output buffers. However, this transient current needs to be provided… Read More
Facing the Quantum Nature of EUV Lithography
The topics of stochastics and blur in EUV lithography has been examined by myself for quite some time now [1,2], but I am happy to see that others are pursuing this direction seriously as well [3]. As advanced node half-pitch dimensions approach 10 nm and smaller, the size of molecules in the resist becomes impossible to ignore for… Read More
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
Dan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior to joining RISC-V International, Gallo worked in leadership roles at Linaro for over a decade. He built Linaro’s server engineering… Read More
Silvaco’s Diffusion of Innovation: Ecosystem Investments Driving Semiconductor Advancements
In Silvaco’s June 2025 Tech Talk, “The Diffusion of Innovation: Investing in the Ecosystem Expansion,” Chief Revenue Officer Ian Chen outlined how strategic partnerships accelerate R&D in semiconductor design and digital twin modeling. As a leading provider of TCAD, EDA software, and SIP solutions,… Read More
CEO Interview with Vamshi Kothur, of Tuple Technologies
It was my pleasure to meet with Vamshi Kothur and the Tuple team at #62DAC for a briefing on their Tropos platform and Omni, a new multi-cloud optimizer. The conferences this year have been AI infused with exciting new technologies but one of the lingering questions is: How will the existing semiconductor design IT infrastructure… Read More
Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs
What if you could reduce power and extend chip lifetime, without compromising performance? We all know the importance of power optimization for advanced SoCs. Thanks to the massive build out of AI workloads, power consumption has gone from a cost or cooling headache to an existential threat to the planet, if current power consumptions… Read More



PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day