Semiwiki Ansys SimWorld

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                    [post_content] => see no evil monkeyIn the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time.

There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, see no evil and speak no evil’. If they were developing SoCs, you wouldn’t want them on your team. They aren’t going to listen to what the monitoring fabric is telling them, they wouldn’t be able to see deep inside their device to understand what was really happening during device bring up or mission mode and they certainly aren’t going to tell you what they haven’t done or if something is wrong.  You’ll be able to see that for yourself when your device comes back from the fab and it’s performance is below the spec’s requirements.

Sometimes turning a ‘blind-eye’ can work out OK. Take a famous nobleman from the Elizabethan times in Britain. Allegedly playing a game of bowls (Francis Drake Wikipedia Page) on Plymouth Hoe, (a few  miles from Moortec’s Worldwide HQ), Sir Francis Drake, an English sea captain, privateer, slave trader, pirate, naval officer and explorer is alleged to have looked at the advancing Spanish Armada off the Plymouth coast and declared there was plenty of time to finish the game. The expression ‘turning a blind eye’ is originally attributed to Admiral Horatio Nelson, who used his injured blind eye when wishing to ignore instructions from his superiors in battle!

SoC development is a complex business. With shrinking geometries and escalating costs, trusting to luck is a dangerous strategy, especially when there are off-the-shelf solutions that will give you much greater visibility into your design.

So Mizaru isn’t a reliable engineer and Nelson and Drake did take the risk…yet there are a lot of casinos in Las Vegas who make a lot of money from those whose luck runs out.  To quote Clint Eastwood in the film Dirty Harry, “You’ve got to ask the question: ‘do I feel lucky?’ Well, do ya, punk?”…with 5nm tape outs running to 10 figures, luck isn’t a viable commodity.

In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE

Watch out for final part of this blog trilogy which will be available in early June, keep and eye on our Social Media pages for more information!

About Moortec
Moortec have been providing innovative embedded subsystem IP solutions for over a decade, empowering customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm and 5nm. Moortec in-chip sensing products support the semiconductor design community’s demands for enhanced performance optimization and increased device reliability, helping to bring product success by differentiating the customers’ technology. With a worldclass design team, excellent support and a rapidly expanding global customer base, Moortec are the go-to leaders in innovative in-chip technologies for the automotive, consumer, high performance computing, mobile and telecommunications market sectors.

For more information please contact Ramsay Allen ramsay.allen@moortec.com, +44 1752 875130, visit www.moortec.com and follow us on Twitter and LinkedIn.
                    [post_title] => Talking Sense With Moortec…See No Evil!
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Moore's Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation. Probably the most well-known scaling limiter for transistors is the short-channel effect (SCE) which has been covered for many years and updated for recent transistor developments like FinFETs. Much less well-known but still very important and persistent is contact resistance, i.e., the electrical resistance of the narrow contact to the much larger transistor. A higher contact resistance is damaging in either of two ways: (1) less current at the same operating voltage, which reduces performance, or (2) higher voltage for the same driving current, which increases power consumption. The contact resistance (Rc) is usually characterized by the "contact resistivity" which actually has the units of resistance x area (ohms-cm^2). The actual resistance is computed from contact resistivity by dividing contact resistivity by the contact area. In Figure 1, the trend of contact resistance is plotted from three different references, published over a period of ten years.
Contact Resistance The Silent Device Scaling Barrier
Figure 1. Contact resistance trends, from various studies from 2008 to 2018 [1-3]. The earliest reference [1] is from 2008, published by Stanford. It was based on projections from the 2005 ITRS roadmap projection at the time. The second reference is from 2013 [2], from an interesting paper discussing the use of an interfacial layer. Half the authors listed were affiliated with Applied Materials, so the data for it on the graph is labeled as "AMAT". The contact resistivity used here was 3.5e-8 ohm-cm^2. The third, most recent reference is from IMEC[3], which presented an atomistic simulation study. Its values are lower than previous projections. Specific assumptions for this case were: n+ doping of 3e20/cm^3, amorphous titanium silicide interface. The resulting calculated resistivity was 4e-9 ohm-cm^2. A lower doping would raise the resistance significantly (Figure 2). For 1e20/cm^3, with over 2 kOhm resistance, even 65 nm size contacts are a problem for many applications.
Contact Resistance The Silent Device Scaling Barrier 2
Figure 2. The contact resistance can be increased significantly by a reduction of doping (from 3e20/cm^3 to 1e20/cm^3 in this case) [3]. The red arrow in the graph marks where we are today at the bleeding edge. At this point, the contact resistance is already over 1.5 kOhm, and this is about 3 times what it was for the 90 nm node. Contact resistivity needs to get to below 1e-9 ohm-cm^2 to avoid becoming prohibitive at ~10 nm scale. Based on IMEC's results [3], this may require doping over 1e21/cm^3, which is 2% concentration impact in silicon! It would not be the original pure silicon anymore! Not surprisingly, the move from planar transistors to FinFETs simultaneously changed the way contacts are landed. They don't land flat on the silicon surface anymore. Instead the contact lands on and wraps around the angled surfaces of epitaxially grown SiGe, which effectively increases the contact area. In a way, transistor contact scaling in 2D already hit the wall, and we are already operating in 3D. Notation clarification: The notation "1e20" is the same as 1 x 10^20. Likewise, "3e-8" means 3 x 10^-8.

References

[1] L. Wei, J. Deng, L-W. Chang, K. Kim, C-T. Chuang, H.-S. P. Wong, "Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap," IEEE Trans. Elec. Dev. 56, 312 (2009). [2] S. Gupta, P. P. Manik, R. K. Mishra, A. Nainani, M. C. Abraham, S. Lodha, "Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts," J. Appl. Phys. 113, 234505 (2013). [3] A. Dabral, G. Pourtois, K. Sankaran, W. Magnus, H. Yu, A. de Jamblinne de Meux, A. K. A. Lu, S. Clima, K. Stokbro, M. Schaekers, N. Collaert, N. Horiguchi, M. Houssa, "Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations," ECS J. Solid State. Sci. and Tech. 7, N73 (2018).
[post_title] => Contact Resistance: The Silent Device Scaling Barrier [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => contact-resistance-the-silent-device-scaling-barrier [to_ping] => [pinged] => [post_modified] => 2020-05-22 08:08:16 [post_modified_gmt] => 2020-05-22 15:08:16 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285706 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 285932 [post_author] => 28 [post_date] => 2020-05-22 10:00:52 [post_date_gmt] => 2020-05-22 17:00:52 [post_content] => ANSYS Simulation WorldANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”. “Simulation World is world’s largest virtual event for research and development leaders and engineering simulation thought leaders and users across industries. Through a series of informative keynote presentations, industry and initiative breakout sessions, attendees will learn the latest innovations and best practices in simulation and its application in sectors ranging from automotive to semiconductor to health care. Interactive chat features will help attendees connect in real time with their colleagues around the world to ask questions and to network. And they can learn about the newest advances in simulation from leading company in a partner pavilion.” There are four semiconductor tracks including four designer presentations which is something ANSYS is well known for with live events such as the Design Automation Conference. Talking about products is one thing, talking about real problems those products solve is quite another, absolutely. Here are the customer presentations: Nitin Navale, CAD Manager, Xilinx Session title: Elastic Compute Scalable Design Methodologies for Next-Generation FPGAs Wednesday, June 10 Dai Dai, Mixed Signal Design Manager, NVIDIA Session title: Optimizing Electromagnetic Crosstalk and Power Distribution for HighSpeed Serial Links on Silicon Wednesday, June 10 Jiaze Li, Senior Engineer, Qualcomm Session title:Novel RTL Power Regression and Minimization Workflow for Mobile GPU Cores Thursday, June 11 Erman Timurdogan, Director, Analog Photonics Session title: Designing Large-Scale Silicon Photonics Integrated Circuits through PDK Component Library Thursday, June 11 You will also want to catch John Lee's keynote: John Lee, Vice President and GM, Semiconductor BU Session title: Reducing Your Project Risk in a Time of Great Change Wednesday, June 10 For those of you who don't know John he is an EDA legend in the making. John started his career Co-founding Performance Signal Integrity, a startup from Carnegie Mellon University. Avant! acquired PSI in 1994 which is where I first met John. Avant! was acquired by Synopsys in 2002. John went on to Co-found Mojave Design, which Magma acquired in 2004, Magma and was acquired by Synopsys in 2012. John then assembled a team that built the first big data platform for chip design which was acquired by ANSYS in 2015. Bottom line: When John speaks you listen, absolutely. And what simulation event would not include academic research: Sung-Kyu Lim,  Professor, Georgia Tech Session title: Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect Thursday, June 11 Makoto Nagata, Professor, Kobe University Session title: A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits Thursday, June 11 To round things out the ANSYS staff of experts weigh in: Ankur Gupta, Senior Director, Application Engineering Session title: Not Your Dad’s Power Integrity Analysis Wednesday, June 10 Anand Raman, Senior Director, Key Global Accounts Session title: Top Electromagnetic Coupling Issues to Watch Out for in High Frequency Silicon Design Wednesday, June 10 Karthik Srinivasan, Sr. Manager, Product Management Session title: Designing High-Speed Memories for the Edge Without Falling Over the Edge Wednesday, June 10 Karan Sahni, Director, Applications Engineering Session title: All things 3D-IC: Taking the Headache out of Managing Multiphysics Codesign for a 3D-Chip Package-System Thursday, June 11 Remember, it is a virtual event so register now and you will get a link to the replay in case you miss it. The SemiWiki bloggers will be all over this event so stay tuned for our expert observations, opinions, and experience on the subject matters. I hope to virtually see you there! Simulation World ANSYS SemiWIki [post_title] => The Largest Engineering Simulation Virtual Event in the World! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-largest-engineering-simulation-virtual-event-in-the-world [to_ping] => [pinged] => [post_modified] => 2020-05-22 13:46:11 [post_modified_gmt] => 2020-05-22 20:46:11 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285932 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 285918 [post_author] => 13 [post_date] => 2020-05-22 06:00:58 [post_date_gmt] => 2020-05-22 13:00:58 [post_content] => If you are like me, you will get a 5G phone because of the high bandwidth it offers. However, there is a lot more to 5G than just fast data. In fact, one of the appealing features of 5G is low bandwidth communication. This is useful for edge devices that perform infrequent and low volume data transfers and depend on long battery life. Prior to 5G many devices relied on 2G or 3G for data transfer which came with very high power requirements and costs, due to cellular overhead. 5G adds support for Narrow Band IoT (NB-IoT) communication for power sensitive devices. However, simply taking a radio architecture designed for higher bandwidth and applying it to NB-IoT leaves a lot to be desired. The best analogy I can come up with is why SUVs initially drove like trucks. If you take a truck chassis and build an SUV on it, what you will get is a car that rides like a truck. Synopsys does a good job of highlighting this in a recent webinar video that introduces their new NB-IoT ARC Communications IP Subsystem for Wireless Narrowband IoT designs. The video was done in conjunction with Santa Clara based Palma Ceia Semidesign who collaborated with Synopsys to develop a complete hardware/software NB-IoT Solution. Rich Collins, PMM at Synopsys for ARC Processors & Subsystems starts by describing what is new and different about 5G’s NB-IoT. Rather than take a wide band cellular LTE modem and adapt it to NB-IoT, Synopsys has taken the approach of eliminating unnecessary hardware and moving much of the functionality into software running on a specifically designed processor. This has many advantages. There is a shortened development cycle for the smaller hardware implementation. It is also more flexible and can easily be adapted to changing standards. Synopsys provides a full software kit to support Base Comms and the NB-IoT User Equipment Stack. 5G NB IoT Processor from Synopsys The processor at the heart of this Subsystem is the ARC EM11D. It combines high efficiency control with ultra low power DSP operations. Its ARC Processor EXtension (APEX) mechanism is useful for adding application specific extensions in the form of hardware RTL. It features a single cycle 16+16 MAC that efficiently supports PHY data processing. There is also a development library with rich DSP functions. The NB-IoT subsystem has many features that enable low power communications. The Digital Front End facilitates integration with RF transceivers. Viterbi and trig functions are handled in hardware through APEX instructions. There are standard AHB/APB busses that help with SoC integration. There are also standard peripheral interfaces that can be used for power management, as well as RF and host connectivity. The subsystem also possesses flexible power management features with customer programmable power modes. Rich talks about the needs of a complete IoT SoC using their IP based system concept. The IoT comms subsystem is combined with tRoot HSM for iSIM to provide SIM functionality and security. An RF transceiver, such as the Palma Ceia PCS NB-IoT Transceiver, eFlash and RAM/ROM round out the system, providing everything needed for a fully functional IoT SoC that can use 5G networks and have standby battery life of over 10 years. At the end of the webinar Rich discusses a demo platform they assembled that shows the feasibility of the complete solution. 5G NB-IoT will be used in medical/fitness devices, smart cities, smart agriculture, industrial automation and many other applications. With the roll out of 5G, NB coverage will be available in places that never had low cost and low power service. There is rapid adoption in the US, Europe and Asia. Undoubtably there will be a high demand for SoCs that support NB-IoT. I’d suggest the Synopsys/Palma Ceia webinar video to anyone who has an interest in this topic. It is available on the Synopsys website and goes into much more detail on the ARC Communications IP Subsystem and RF transceiver. [post_title] => Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => synopsys-announces-ip-supporting-5gs-game-changing-low-power-iot-spec [to_ping] => [pinged] => [post_modified] => 2020-05-21 19:29:43 [post_modified_gmt] => 2020-05-22 02:29:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285918 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 285868 [post_author] => 16 [post_date] => 2020-05-21 06:00:02 [post_date_gmt] => 2020-05-21 13:00:02 [post_content] => I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it. They’re hosting a webinar on May 28th 10-11am PDT (REGISTER HERE) in which Atos talk about how they use the tool in building a proof of concept for the MontBlanc 2020, a European HPC processor architecture. Mont Blanc This processor architecture is a scalable array of cores, interconnected through a NoC mesh connecting a crosspoint and protocol component at each core. This is a perfect application for the Defacto platform. All the design and architecture smarts are in Atos, however scripting assembly in SystemVerilog taking full advantage of parameterized interfaces can be very messy – as any designer script enthusiast knows. That’s where Defacto adds value, by handling that SV complexity while still allowing full freedom for Atos to script what they want. The speaker (Laurent Marliac from Atos) mentioned that in their case, they can have up to 64 cross points in the mesh, each with up to 100 parameters to be configured, and each with complex configurable connectivity between cells in the array. Manually creating this in SV makes no sense and anyway isn’t the architecture/design value-add in the process. Defacto lets the design team define what they want through their own YAML scripts, from which they generate two Tcl files, one to drive RTL generation for the NoC top-level and one to drive generation of a testbench for that NoC. All the design intent and experience is in the Atos YAML scripts and their translation to Defacto Tcl or Python commands. Once this scripting and flow has been set up, Laurent says that while figuring out what they want to change in the YAML takes thought and time, generation of a new NoC and testbench through the rest of the flow takes only a few seconds. Laurent also mentioned that they are using DeFacto not only for the NoC but also pad ring generation and DFT module generation, each of which has to scale flexibly as the processor array scales. This makes a lot of sense to me. In fact I wish I’d thought of it when we were promoting GenSys at Atrenta (our somewhat equivalent tool). Scalable components like NoCs and scalable systems like the MontBlanc 2020 are perfect applications for an automation tool to connect designer/architect scripting to SystemVerilog RTL generation. The mistake we made was to try to own as much as possible of the generation flow, which really wasn’t possible given the complexity of product engineering, architecture and design needs. Pad rings are a perfect example. We wanted engineers to fill out a highly complex spreadsheet to describe all the IO muxing, pad cell types and selection controls, but that’s impossible. Needs vary too widely even between product groups within the same company. Defacto doesn’t try to manage that part. Engineers can build their own spreadsheets and scripts, then let Defacto deal with the SV end of the problem. For anyone planning to automate parts of their design construction, this will be a must-watch. Remember to REGISTER HERE to watch the webinar on May 28th 10-11am PDT. [post_title] => Atos Crafts NoC, Pad Ring, More Using Defacto [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => atos-crafts-noc-pad-ring-more-using-defacto [to_ping] => [pinged] => [post_modified] => 2020-05-23 09:29:25 [post_modified_gmt] => 2020-05-23 16:29:25 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285868 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 285616 [post_author] => 11830 [post_date] => 2020-05-20 14:00:54 [post_date_gmt] => 2020-05-20 21:00:54 [post_content] => If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that. The Silicon Valley chapter of SEMI is presenting a webinar entitled: WAFERS TO WALL STREET—A Semiconductor Outlook: Emerging Markets & Technologies and the Impact of COVID-19 on the Supply Chainon June 25, 2020 from 8:00 AM to 10:45 AM Pacific Daylight Time. This event looks like it will deliver a lot of great information. Before I get into that, a bit about the organizer. In its words, SEMI is a “global industry association serving the product design and manufacturing chain for the electronics industry.” The organization has over 2,300 member companies and 1.3 million individual members. I’ve been to many SEMI-run events over the years and I can tell you they are relevant, well-run and informative. The upcoming event promises to deliver an important and unique perspective. We all know the semiconductor industry is influenced by a complex balance of financial results, ecosystem interactions and market performance (both existing and emerging). You need to take all that into account to try and figure out what will happen next. This event brings together a panel of speakers that can address all those aspects. The top-level agenda of the event includes:
  • Market Outlook, Technology Trends, Market Indicators and Drivers
  • Impact of Emerging Technologies on Regional & Global Economies
  • Impact of COVID-19 on the Electronics Supply Chain
  • Trends for Fab Investments and Capacities
  • Materials and Advanced Packaging Opportunities and Challenges
  • Integration Technologies
  • Q&A Session
That’s a lot to deliver. Let’s look at who will be presenting: Jan Gaudested: Vice President, Business Development, Wooptix, a light field imaging company headquartered in Tenerife, Spain, developing advanced technology for the semiconductor metrology equipment market. John Pitzer: Managing Director, Global Technology Strategist, Technology Sector Head and Semiconductor Analyst for Credit Suisse Group. Mr. Pitzer has a lot of excellent credentials regarding the semiconductor capital equipment market. Godfrey Cheng: Head of Global Marketing, TSMC. TSMC needs no introduction. Prior to TSMC, Mr. Godfrey led various corporate, product and technical marketing functions at ATI Technologies and AMD. Wenge Yang: Vice President, Market Strategy, Entegris. Dr. Wang has been leading product and market strategy, market research and market trend analysis, strategic marketing, and the strategic technology roadmap for Entegris since 2012. Previously, he was an equity research analyst at Citigroup covering the semiconductor equipment and materials sector. Dr. Yang received a PhD in Materials Science and Engineering and an MBA from Rensselaer Polytechnic Institute. Christian Gregor Dieseldorff: Senior Principal, Industry Research and Statistics Semiconductors, SEMI HQ. Before joining SEMI in 2007, Mr. Dieseldorff led engineering efforts at places like Siemens, IBM, International Sematech and Infineon. Carolin Seward: Vice President & General Manager, Data Center Solutions Group, Intel. She is responsible for delivering integrated data center solutions with the best customer experience for the lifecycle of the product. Previously, Carolin was Vice President in the Technology and Manufacturing Group and Director of Global Supply Management at Intel. Katsumi Hoashi: Vice President, Corporate Strategic Planning, TDK. Haoshi-san has 20 years of management experience in system LSI products in the consumer market. He has also worked at TDK, Socionext and Panasonic. Yin Chang: Senior Vice President, Sales & Marketing, ASE Group Global. Mr. Chang is responsible for developing and executing sales strategy and marketing activities for ASE’s expanding packaging, systems, and integration solutions portfolio. He has a long history of working on advanced packaging technologies. As you can see, all aspects of the forces that influence the semiconductor market will be covered at this event, from financial to equipment, ecosystem and technology/markets. Learn more about the event and sign up here. I plan to attend, and I hope you will as well. [post_title] => A Thoughtful Semiconductor Outlook – Needed Now More Than Ever [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => a-thoughtful-semiconductor-outlook-needed-now-more-than-ever [to_ping] => [pinged] => [post_modified] => 2020-05-27 08:57:17 [post_modified_gmt] => 2020-05-27 15:57:17 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285616 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 285779 [post_author] => 17944 [post_date] => 2020-05-20 10:00:24 [post_date_gmt] => 2020-05-20 17:00:24 [post_content] => The current Coronavirus crisis is inflicting a lot of pain on people, companies, and governments. I hope I am not getting in trouble with my reasoning, but if you look closely, there are also some “positives” to the Covid-19 crisis. - It is stress-testing our infrastructure and telling us where we need to improve – as country, states, communities, companies, and individuals – to benefit long-term. - Empty shelves and/or purchase quantity limits at grocery stores show us the importance of a solid supply chain. - Extremely high demand for laptops, iPads, video cameras, and other essentials for working remotely, tell us that High-Tech is a great industry to work for and that we have a lot of opportunities for growth – if we get the pricing right. Allow me to pick up on “getting the pricing right” and outline some ideas how to streamline the High-Tech supply chain, to further lower the cost of electronic products, make it easier to set up home offices and grow our revenues and profits. From 1980 until ’96 I worked in the manufacturing part of the semiconductor supply chain, at two big IC vendors. Since 1997 I am in the Electronic Design Automation (EDA) portion, focused on encouraging the use of EDA tools to make semiconductor manufacturing more efficient and more cost-effective, by broadening the collaboration between EDA and manufacturing experts. EDA and wafer foundry experts have made remarkable progress in the last forty years. For example: in 1980 I sold my first ASIC at two cents per gate; today two cents buy you at least one Million gates. Excellent collaboration between material suppliers, equipment vendors, wafer foundries as well as EDA, IP and IC design experts made such progress possible. Figure 1 shows a significantly simplified Collaboration Flow between the essential parties. They have enabled in the last four decades enormous IC complexity increases, broadened the range of functionalities and, at the same time, reduced cost per function by six orders of magnitudes. Figure 1 Foundry  Figure 1 Collaboration with Foundry During the 2008 financial crisis, rumors about the end of Moore’s Law and the need for More than Moore started. I took this as an opportunity to change my focus from the traditional single-die SoC technology to multi-die ICs (2.5/3D-ICs). In these new technologies the package adds a lot of value to the complete solution. Until that time, I was used to being part of the broad and in-depth cooperation between EDA vendors and wafer foundries, developing Process Design Kits (PDKs) and Reference Design Flows. That’s the reason why I was surprised that IC assembly/test houses (a.k.a. OSATs), at that time, were not as proactive as wafer foundries. They had no design kits, nor reference flows, and the excellent engineers at the OSATs had to spend a lot of manual efforts, to meet their customers’ IC packaging and cost requirements. Thanks to industry organizations, like the Global Semiconductor Alliance (GSA), SEMATEC, the Silicon Integration Initiative (Si2), the Electronic System Design Alliance (ESDA), MEPTEC and SEMI, who gave me “a soap-box” to better highlight the industry’s pressure for more automation between IC designers and OSATs, several OSATs have developed since, in cooperation with their EDA partners, Assembly Design Kits (ADKs) and Design Reference Flows for packages. Figure 2 shows a significantly simplified Collaboration Flow between the essential parties, to reduce package development time and engineering cost. Please, DO NOT plan on six magnitudes in package unit cost reduction. To achieve this target, IC packages would need to be shrunk so much, that nobody could see or use them anymore. Figure 2 OSAT Figure 2 Collaboration with OSAT Bottom Line: Assembly Design Kits and Design Reference Flows encourage the use of off-the-shelf or “pre-customized” packages. Yes, they do limit IC designers’ flexibility somewhat, but the significant savings in development time and engineering cost, as well as lower manufacturing cost will reward IC Vendors and OSATs royally for streamlining/automating their collaboration. Best of all, ADKs and Reference Flows make IC package design and manufacturing very scalable!!! [post_title] => Collaboration Flow for Moore’s Law versus More than Moore [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => collaboration-flow-for-moores-law-versus-more-than-moore [to_ping] => [pinged] => [post_modified] => 2020-05-21 06:33:19 [post_modified_gmt] => 2020-05-21 13:33:19 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285779 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [7] => WP_Post Object ( [ID] => 285796 [post_author] => 28 [post_date] => 2020-05-20 06:00:21 [post_date_gmt] => 2020-05-20 13:00:21 [post_content] => Flex Logix Inference AccellerationeFPGA is now widely available, has been used in dozens of chips, is being designed into dozens more and it has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or market needs are changing. FPGAs can also accelerate many workloads faster than processors. For example, Microsoft Azure uses one FPGA accelerator for every 2 Intel Xeons. Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node. The EFLEX eFPGA is silicon proven in 40nm down to 12nm with 7nm in process. WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible! In this webinar Andy Jaros talks about the emergence of eFPGA over the last five years and the success of Flex Logix amongst multiple market segments. Here is a quick update from their website: "We are solidly funded and backed by strong Venture Capitalists Lux and Eclipse. We have proven our eFPGA technology in 180nm, 40nm, 28/22nm, 16nm and 12nm with TSMC and GlobalFoundries. There are more than 10 working SoCs with our technology and >>10 more in fab/design.  Our customers are very well funded organizations and companies and our technology is strategically critical to them.  Our cash in the bank and our backlog/commitments mean that we do not need to raise cash in 2020 and we can fund our AI Inference chip development and production ramp from cash flow. Our AI chip, InferX X1, benchmarks with superior price/performance on real-world neural network models customers have given us. As X1 ramps production our financial situation will be even stronger." Andy Jaros is one of my trusted few. He is the VP of Sales and Solutions Architecture at Flex Logix. Andy has more than 30 years of semiconductor experience most of which involves IP, most notably ARC, Virage Logic, and Synopsys. I was at Virage when we acquired ARC and that is where I first met Andy, who is also a neighbor of mine. He continued on with Synopsys after they acquired Virage and then moved to Flex Logix more than 4 years ago. At that time eFPGA was just another acronym. Today, Flex Logix is the leading provider of embedded FPGA hard IP and software. Flex Logix is also launching Inference Acceleration chips for Edge Applications so they are not just an IP company. Flex Logix came to SemiWiki four years ago and we have now published 40 blogs with them that have earned more than 250,000 views. Excellent content gets excellent views, absolutely. The webinar is coming up so register now: WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible! Here are the questions I have for Andy. If you have others let me know: What is the area penalty for using an eFPGA? How does the eFPGA get programmed and by who? What specific design considerations do you need to make for eFPGA use?     [post_title] => eFPGA - What’s Available Now, What’s Coming and What’s Possible! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => efpga-whats-available-now-whats-coming-and-whats-possible [to_ping] => [pinged] => [post_modified] => 2020-05-20 08:35:16 [post_modified_gmt] => 2020-05-20 15:35:16 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285796 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 7 [filter] => raw ) [8] => WP_Post Object ( [ID] => 285846 [post_author] => 15 [post_date] => 2020-05-19 10:00:20 [post_date_gmt] => 2020-05-19 17:00:20 [post_content] => TSMC US Fab SemiWiki On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.” The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction is planned to start in 2021 and production is targeted for 2024. Total spending on the project including capital expenditure will be $12 billion dollars between 2021 and 2029. This announcement is undoubtedly the result of intense pressure on TSMC by the US government and it is also coming out today that TSMC will stop taking orders from Huawei also under pressure from the US. What does this fab announcement mean? This announcement is in my opinion soft, “Intention to build”, “construction planned to start”, “production targeted”. The project is based on a “mutual understanding and commitment to support from the U.S. federal government and the State of Arizona”, What happens if Donald Trump is voted out in November or just changes his mind? I could easily see this project never materializing due to changes in the US political situation or lack of follow-through from TSMC who is likely not excited about it to begin with. My company IC Knowledge LLC is the world leader of cost and price modeling of semiconductors and MEMS. I thought it would be interesting to use our Strategic Cost and Price Model to make some calculations around this fab. TSMC operates four major 300mm manufacturing sites in Taiwan and one in China. The four sites in Taiwan are all GigagFab sites, Fab 12, Fab 14, Fab 15 and Fab 18 are each made up of 6 or 7 wafers fabs sharing central facility plants. This Gigafab approach is believed to reduce construction costs by about 25% versus building a single stand-alone fab. The china fab location is smaller with 2 fabs at one location but the fab was equipped with used equipment transferred from fabs in Taiwan because the fab is trailing edge. If TSMC really builds a single US fab running 20,000 wpm the resulting cost to produce a wafer will be roughly 1.3% higher than for a GigaFab location due to higher construction costs. I believe it is unlikely the site will be equipped with used equipment transferred from Taiwan. The cost to build and equip the fab for 20,000 wpm should be approximately $5.4 billion dollars. Locating a fab in the US versus Taiwan will result in the fab incurring US labor and utility costs, this will add approximately 3.4% to the wafer manufacturing cost. The capacity of the fab is also smaller than a “typical” fab at advanced nodes, the three 5nm fabs TSMC is operating or planning for Taiwan are all 30,000 wpm. A 20,000 wpm fab will have an approximately 3.8% increase in costs versus a 30,000 wpm fab under the same conditions. In total, wafers produced at the TSMC Arizona fab will be approximately 7% more expensive to manufacturer than a wafer made in Fab 18 in Taiwan. This does not account for the impact of taxes that are likely to be higher in the US than in Taiwan. In the announcement TSMC has said the total spending on the project between 2021 and 2029 would be $12 billion dollars. That leaves money for a future expansion or conversion to 3nm. That would be almost enough money to add a second 20,000 wpm fab running 3nm as one possible example. In summary the “announced” fab would likely be TSMC’s highest cost production site. It will be interesting to see if the fab materializes. [post_title] => Cost Analysis of the Proposed TSMC US Fab [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => cost-analysis-of-the-proposed-tsmc-us-fab [to_ping] => [pinged] => [post_modified] => 2020-05-19 08:56:17 [post_modified_gmt] => 2020-05-19 15:56:17 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285846 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 29 [filter] => raw ) [9] => WP_Post Object ( [ID] => 285506 [post_author] => 16 [post_date] => 2020-05-19 06:00:43 [post_date_gmt] => 2020-05-19 13:00:43 [post_content] => Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree. innovation The Innovation This month’s pick is Which Software Faults Are Tests Not Detecting? The paper was presented at the 2020 Evaluation and Assessment in Software Engineering conference. The authors are all from Lancaster University in the UK. The contribution in this paper is analysis of testing efficiency in software, to find methods to improve the ability of tests to uncover more bugs. The authors measure efficiency through a combination of code coverage and mutation analyses. In mutation testing functional errors are inserted in the code, testing is re-run and test efficiency is determined by ability to detect the mutation. They apply their analysis to 10 open-source systems with associated unit tests, using a tool to automatically insert faults. From this they analyze efficiency of the tests by fault type. They report that in 6 of the systems, less than 50% of the injected faults are detected and some fault types are detected more frequently than others, particularly conditional boundary checks. They also find that the lowest performing tests are 10X less efficient in detecting boundary faults. The authors also discuss challenges in mutation testing. One study finds that most post-release faults are complex and can only be fixed through modifications in several locations. Attempting to model these through mutation would explode rapidly. Also, a study at Google confirms that even simple mutation testing is very expensive. Many mutants are unproductive, being either redundant or equivalent, yet are not easily weeded out. Paul This is something we’re looking at closely as a natural area of interest in our metric driven verification (MDV) strategy. We’re always interested in ways to help improve test effectiveness; this paper adds to our understanding. Testing mutated code is computationally expensive, whether it’s software or hardware, since you have to run all your tests not only on the original code but also on each mutated version. In hardware verification, testing the non-mutated design is already swamping verification resources. If we are going to do mutation testing in hardware, we need to focus on high ROI mutations. A second concern is that mutation testing exposes limitations in tests, not bugs in the design. Which is still valuable but not a first-order concern, making it a tougher sell for schedule-constrained projects. Nevertheless, selective use of high ROI mutation coverage could still be helpful in hardware, especially for modules where there is no good functional coverage model available. The paper cites boundary condition mutation, for example, mutating “<=” with “<” as more likely to find useful gaps in tests than mutating “+” with “-“.  Buffer overflow security attacks are given as a good example where boundary condition mutation can catch gaps in test suites. This example applies equally to both software and hardware test. Very thought-provoking. Jim The observation I want to make here, as an investor is that I have seen a decline in research in functional verification at the RTL level, at least judging by the number of papers we see. Not application-level stuff, how to better use the tools we’ve already got, that’s common. I’m talking about original research, from universities or outfits like Google. This isn’t because all the problems are solved – they definitely aren’t. I think it’s more for universities because grants are directed to problems in other areas, and in the hyperscalars because software is their biggest driver for innovation. What then should we do in functional verification for hardware? Learn from research in software verification! The two domains are very closely related, not identical but the overlap is significant. I want to see more of these software parallels. On this topic specifically, I want to better understand the associated costs. That’s a huge factor in ROI; the “R” will have to be equally impressive. Me Security seems like a good application for mutation testing. Here there may be more willingness to accept the added overhead, also the recently released Mitre list of common weaknesses in hardware should provide inspiration for more security-related high-value mutations beyond boundary conditions. To see the previous paper click HERE. [post_title] => Is Mutation Testing Worth the Effort? Innovation in Verification [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => is-mutation-testing-worth-the-effort-innovation-in-verification [to_ping] => [pinged] => [post_modified] => 2020-05-19 08:36:43 [post_modified_gmt] => 2020-05-19 15:36:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=285506 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 5 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 285929 [post_author] => 29972 [post_date] => 2020-05-24 10:00:52 [post_date_gmt] => 2020-05-24 17:00:52 [post_content] => see no evil monkeyIn the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, see no evil and speak no evil’. If they were developing SoCs, you wouldn’t want them on your team. They aren’t going to listen to what the monitoring fabric is telling them, they wouldn’t be able to see deep inside their device to understand what was really happening during device bring up or mission mode and they certainly aren’t going to tell you what they haven’t done or if something is wrong.  You’ll be able to see that for yourself when your device comes back from the fab and it’s performance is below the spec’s requirements. Sometimes turning a ‘blind-eye’ can work out OK. Take a famous nobleman from the Elizabethan times in Britain. Allegedly playing a game of bowls (Francis Drake Wikipedia Page) on Plymouth Hoe, (a few  miles from Moortec’s Worldwide HQ), Sir Francis Drake, an English sea captain, privateer, slave trader, pirate, naval officer and explorer is alleged to have looked at the advancing Spanish Armada off the Plymouth coast and declared there was plenty of time to finish the game. The expression ‘turning a blind eye’ is originally attributed to Admiral Horatio Nelson, who used his injured blind eye when wishing to ignore instructions from his superiors in battle! SoC development is a complex business. With shrinking geometries and escalating costs, trusting to luck is a dangerous strategy, especially when there are off-the-shelf solutions that will give you much greater visibility into your design. So Mizaru isn’t a reliable engineer and Nelson and Drake did take the risk…yet there are a lot of casinos in Las Vegas who make a lot of money from those whose luck runs out.  To quote Clint Eastwood in the film Dirty Harry, “You’ve got to ask the question: ‘do I feel lucky?’ Well, do ya, punk?”…with 5nm tape outs running to 10 figures, luck isn’t a viable commodity. In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE Watch out for final part of this blog trilogy which will be available in early June, keep and eye on our Social Media pages for more information! About Moortec Moortec have been providing innovative embedded subsystem IP solutions for over a decade, empowering customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm and 5nm. Moortec in-chip sensing products support the semiconductor design community’s demands for enhanced performance optimization and increased device reliability, helping to bring product success by differentiating the customers’ technology. With a worldclass design team, excellent support and a rapidly expanding global customer base, Moortec are the go-to leaders in innovative in-chip technologies for the automotive, consumer, high performance computing, mobile and telecommunications market sectors. For more information please contact Ramsay Allen ramsay.allen@moortec.com, +44 1752 875130, visit www.moortec.com and follow us on Twitter and LinkedIn. [post_title] => Talking Sense With Moortec…See No Evil! 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Talking Sense With Moortec…See No Evil!

Talking Sense With Moortec…See No Evil!
by Tim Penhale-Jones on 05-24-2020 at 10:00 am

see no evil monkey

In the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time.

There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, … Read More


Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am

Contact Resistance The Silent Device Scaling Barrier

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.

Read More

The Largest Engineering Simulation Virtual Event in the World!

The Largest Engineering Simulation Virtual Event in the World!
by Daniel Nenni on 05-22-2020 at 10:00 am

ANSYS Simulation World

ANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”.

“Simulation World is world’s largestRead More


Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec

Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec
by Tom Simon on 05-22-2020 at 6:00 am

5G NB IoT Processor from Synopsys

If you are like me, you will get a 5G phone because of the high bandwidth it offers. However, there is a lot more to 5G than just fast data. In fact, one of the appealing features of 5G is low bandwidth communication. This is useful for edge devices that perform infrequent and low volume data transfers and depend on long battery life. Prior… Read More


Atos Crafts NoC, Pad Ring, More Using Defacto

Atos Crafts NoC, Pad Ring, More Using Defacto
by Bernard Murphy on 05-21-2020 at 6:00 am

Mont Blanc

I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it.

They’re hosting a webinar on May 28th 10-11am… Read More


A Thoughtful Semiconductor Outlook – Needed Now More Than Ever

A Thoughtful Semiconductor Outlook – Needed Now More Than Ever
by Mike Gianfagna on 05-20-2020 at 2:00 pm

Screen Shot 2020 03 09 at 7.22.59 PM

If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that.

The Silicon… Read More


Collaboration Flow for Moore’s Law versus More than Moore

Collaboration Flow for Moore’s Law versus More than Moore
by Herb Reiter on 05-20-2020 at 10:00 am

Figure 1 Foundry

The current Coronavirus crisis is inflicting a lot of pain on people, companies, and governments. I hope I am not getting in trouble with my reasoning, but if you look closely, there are also some “positives” to the Covid-19 crisis.

– It is stress-testing our infrastructure and telling us where we need to improve – as country,… Read More


eFPGA – What’s Available Now, What’s Coming and What’s Possible!

eFPGA – What’s Available Now, What’s Coming and What’s Possible!
by Daniel Nenni on 05-20-2020 at 6:00 am

Flex Logix Inference Accelleration

eFPGA is now widely available, has been used in dozens of chips, is being designed into dozens more and it has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or market needs are changing. FPGAs can also accelerate… Read More


Cost Analysis of the Proposed TSMC US Fab

Cost Analysis of the Proposed TSMC US Fab
by Scotten Jones on 05-19-2020 at 10:00 am

TSMC US Fab SemiWiki

On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”

The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction… Read More


Is Mutation Testing Worth the Effort? Innovation in Verification

Is Mutation Testing Worth the Effort? Innovation in Verification
by Bernard Murphy on 05-19-2020 at 6:00 am

innovation

Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.

The Innovation

This month’s pick is Which Software Read More