As edge AI systems become more centralized and compute-dense, on-chip data movement is increasingly the architectural bottleneck. NXP’s expanded deployment of Arteris network-on-chip (NoC) and cache-coherent interconnect IP highlights a broader industry trend: interconnect architecture is now a first-order design … Read More
Agentic AI Demands More Than GPUsAgentic AI workloads are reshaping the compute requirements…Read More
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the IncentivesMarc Evans, Director of Business Development & Marketing,…Read More
yieldWerx Delivers a Master Class in Co-Packaged Photonics ImplementationWe all know the semiconductor industry is seeing…Read MoreArchitecting Intelligence: The Rise of RISC-V CPUs in Agentic AI Infrastructure
SiFive’s newly announced $400 million Series G financing represents a significant technical inflection point for high-performance RISC-V CPU development targeted at agentic AI data center workloads. The funding, which values the company at $3.65 billion, is specifically intended to accelerate next-generation CPU IP, … Read More
Intel, Musk, and the Tweet That Launched a 1000 Ships on a Becalmed Sea
Intel, Musk, and the Tweet That Launched a 1000 Ships on a Becalmed Sea
Why do professional executives running major corporations frame a major moment in their company’s history with a tweet? Jerry Sanders spent his career yelling “real men have fabs!” Now Intel has fabs–and apparently tweets about … Read More
From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration
Modern automotive electronics are undergoing a rapid transformation driven by increasing compute demands, functional safety requirements, and the shift toward scalable semiconductor architectures. One of the most significant technological developments enabling this transformation is the adoption of multi-die system… Read More
Agentic AI Demands More Than GPUs
Agentic AI workloads are reshaping the compute requirements of modern data center infrastructure by shifting performance bottlenecks from GPU-centric inference to CPU-heavy orchestration and workflow management. Traditional AI inference pipelines relied primarily on GPUs performing a single forward pass, where input… Read More
Accellera Updates at DVCon 2026
Lu Dai (chair of Accellera) and I had our regular chat at DVCon U.S. 2026. Accellera also hosted a reception in the exhibits hall, with free snacks and drinks, very well attended. We talked about what’s new in Accellera, with a particular emphasis on the recently released standard for CDC and RDC tool interoperability, also Lu’s … Read More
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
Marc Evans, Director of Business Development & Marketing, Andes Technology USA
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More
An Upper Bound on Effective Quantum Computation?
You may think that quantum theory is fully understood but that view is not quite right. There remain open questions around the uncertainty principle, wave-particle duality, measurement collapse, and harmonizing quantum mechanics and gravitation. These concerns may seem very abstract and irrelevant to everyday applications… Read More
WEBINAR: Beyond Moore’s Law and The Future of Semiconductor Manufacturing Intelligence
The semiconductor industry faces unprecedented challenges as it pushes toward advanced nodes below 3nm, managing exponential process complexity, yield variability, and escalating production costs.
This webinar explores the transition from reactive automation to autonomous manufacturing, bringing together leaders… Read More
yieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation
We all know the semiconductor industry is seeing a new era of data intensity. The industry’s response includes advanced semiconductor design strategies, the adoption of chiplets, and the integration of optical I/O and photonics to enable higher performance, faster AI computation, and increased modularity. Co-packaged photonics… Read More



Intel, Musk, and the Tweet That Launched a 1000 Ships on a Becalmed Sea