How to prevent Electrical Overstress failure in NFC interfaces

Last year, about 40% of new smartphones included Near Field Communication (NFC). Analysts predict that by 2017 there will be 1 billion NFC enabled phones. Clearly, the use of NFC is ramping up because it can simplify aspects as diverse as communication, secure payments, user authentication, and retail loyalty programs for instance.

A typical, simplified NFC approach: Near field (max. 10m) communication between 2 devices.

Adding NFC functionality to an integrated circuit involves connecting the wireless interface pins to an antenna/coil. The voltage on those pads strongly depend on the distance between and alignment of transmit/read devices and the power of the transmitting device. Simulations by one of our customers showed a worst case of almost 10V between pads, which is rather high for advanced CMOS technology.

There are basically 2 ways to cope with this excess voltage.

Use high voltage transistors
Designers can use transistors that tolerate voltage up to 10V. Fortunately, many NFC applications also require on-chip non-volatile memory (NVM). Such NVM circuits typically use a thicker gate oxide and foundries provide high voltage transistors for such embedded flash process flavors. Many companies use those NVM transistors for the first stage of the antenna circuit. The problem is that these high voltage transistors are easily damaged during electrostatic discharge (ESD) stress. A parallel on-chip ESD protection circuit (with ~10V tolerance) is the easiest solution.

Because high voltage (memory) transistors are typically rather weak during ESD stress it may be best to use a local ESD protection clamp in parallel.

Limit the voltage
It is possible to reduce the excess voltage with a so-called clipping or limiting circuit. The simple approach is to use a set of diodes.

Simple clipping variations based on diodes.

Other options include clipping or limiting circuits based on transistors. Check out this case study with a clipping circuit.