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Verification Engineer

Verification Engineer
by Admin on 06-23-2020 at 10:05 am

  • Full Time
  • US

Website SmartDV

  • 2-7+ Years of experience in ASIC verification
  • Should have tapped out atleast 1 chips from specs to post silicon debug
  • Should have experience in creating testbenches from scratch
  • Should have very good understanding of coverage driven verification closure
  • Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman))
  • Very good experience in writing scripts in Perl or Python or TCL
  • Independent team player with excellent communication skills
  • Knowledge of C++
  • Preference is given for students from IIT and NIT’s
Apply for job

To view the job application please visit www.smart-dv.com.