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Verification Engineer

Verification Engineer
by Admin on 04-19-2022 at 3:49 pm

  • Full Time
  • US

Website SmartDV

  • 2-7+ Years of experience in ASIC verification
  • Should have tapped out atleast 1 chips from specs to post silicon debug
  • Should have experience in creating testbenches from scratch
  • Should have very good understanding of coverage driven verification closure
  • Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman))
  • Very good experience in writing scripts in Perl or Python or TCL
  • Independent team player with excellent communication skills
  • Knowledge of C++Preference is given for students from IIT and NIT’s

SmartDV offers a unique opportunity for ambitious ASIC engineers. As a ASIC design and verification expert you will have range of projects to work with. You will have opportunity to work with industry’s best talent.

At SmartDV you will get to work on technologies which are very innovative and will have chance to contribute to this innovative technologies. If you think you know next big thing in verification, or you think you can solve next big issue in verification, then SmartDV is right place for you. Send your resume to

Apply for job

To view the job application please visit

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