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(Japan) APR Engineer/Manager

(Japan) APR Engineer/Manager
by Daniel Nenni on 08-15-2020 at 6:25 pm

Website TSMC

1. Physical implementation of advanced technology chips.

2. Be responsible for chip implementation and signoff closure of customer’s projects or internal system test chips.

3. Be Familiar with design methodology development and innovation for advanced technology challenges.

4. Be responsible for advanced node PPA benchmark, and solution development.

5. Customer onsite/offsite supports will be required on demand.

6. Tape-out project management.

 

Work location: Yokohama, Japan

Qualifications
1. Can do APR hands-on work is a must.

2. BCH degree and above in EE, CS related fields.

3. Experienced in APR, physical verification, chip implementation, or CAD development.

4. Familiar with Synopsys/Cadence APR tools/flows.

5. Familiar with TCL/Perl/Python/C++ programming.

6. Advanced process (N16 and beyond) project tape-out experience is much preferred.

7. Good command of Japanese. Fluent in English is a plus.

 

– Specific Requirement:

1. APR Engineer

(1) Seniority 3-10 years

(2) Full chip integration experience is a plus.

2. APR Lead Manager:

(1) Seniority 10-15 years.

(2) Full chip partition/integration experience is a must.

(3) Experience of tape-out management is a must.

Apply for job

To view the job application please visit tsmc.taleo.net.