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Technical Manager

Technical Manager
by Daniel Nenni on 07-15-2020 at 12:59 pm

  • Full Time
  • San Jose, CA
  • Applications have closed

Website TSMC

Role: In this role, the candidate will lead the design of key functional blocks in memory testchip and memory IP.  The candidate will also lead the definitions of memory architecture, application spec and testing requirement.


Design full custom read and write circuits for memory operation.

Simulate, verify and analyze functionality and performance of memory array using statistical design flow.

Evaluate and optimize memory architecture
Design sense amplifier and on-die LDO circuit and supply system.

Design fault-tolerant circuits, including repair and error correction circuit, and built-in-self-test (BIST) circuit.

Develop testing methodology

Qualifications Requirements:

Candidate must have a M.S. + 5 years of working experience or a Ph.D. degree in electrical engineering with experiences on memory circuit design or memory technology development.

Having a good track record on delivering memory testchips, products and technology development is a plus.

Technical expertise on CMOS digital, analog, and memory circuit design using commercial TCAD tools.

Good knowledge of memory circuit design, including SRAM, DRAM, NAND or emerging memories such as MRAM, RRAM or FeRAM.

Good knowledge on memory product design and physical design methodologies.  Experience on memory product development is a plus.

Logical thinking.

Good Verbal and written communication skills
Interpersonal skills, ability to prioritize work/multitask.

Good analytical and problem solving skills.

trong execution mindset.

Fluent in either Chinese and English.

TSMC Technology Inc. is an Equal Opportunity Employer.

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