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Principal Engineer

Principal Engineer
by Daniel Nenni on 09-07-2020 at 8:59 pm

Website TSMC

Design, verify and control quality of SRAM (Static Random Access Memory) memory circuits and compiler timing and power characterization, and IR/EM (voltage drop analysis, voltage/electro-migration) flow. Perform read, write and race margins for robust operation of memories across all operating conditions. Write measurements and vectors for timing characterization.

Require: Master’s degree in Electrical Engineering; 2 years’ experience in job offered or as Design Engineer; experience in validation and timing & power characterization for memory compilers, and IR/EM analysis. Will accept any suitable combination of education, training, or experience.

Work site/mail resume to: TSMC Technology, Inc., 2851 Junction Ave., San Jose, CA 95134.

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