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(Japan) Memory Design Engineer or Manager

(Japan) Memory Design Engineer or Manager
by Daniel Nenni on 07-07-2020 at 10:30 am

  • Full Time
  • Japan

Website TSMC

Description
SRAM architecture design
Read and write critical path design and analysis
Design of key building blocks (sensing, analog, high voltage, DFT)
Chip-level design verification
Embedded non-volatile memory compiler and productization
Co-work with product/reliability engineer on silicon characterization and reliability qualification
Work location: Yokohama, Japan.

Qualifications
Requirements:

The candidates should have at least bachelor degree with 10 years of experiences, master degree with 3 years of experience or PhD degree in relevant field.
Memory experts in the field of SRAM.
Familiar with bit cell characteristics (Vmin, bit cell performance, write margin), sense amplifier design, high sigma variation analysis, race check, margin signoff.
Knowledge on high speed and low Vmin design is a plus.
Good command of Japanese.
English is a plus.

Personal Attributes:

-Self-motivated in learning and problem-solving

-Good communication skill and a good team player

-Strong ownership and commitment

TSMC Technology is an Equal Opportunity Employer.

Apply for job

To view the job application please visit tsmc.taleo.net.