Standard Cell Kits Gen Engineer
Website TSMC
Description
1.Responsible for Stdcell library production schedule commitment
2.Resource management to secure every release schedule
3.Continuously searching efficient enhancement for library Characterization and Kits generation
4.Big Data analysis to clarify advanced technology impact
Qualifications
1.We are looking for talents in the areas of VLSI design flow and chip sign-off process.
2.Familiarity with design and characterization tool in EDA house like Cadence, Synopsys, and Mentor
3.Understanding of basic library characterization concept
4.CS and EE master or PhD title is a must
5.Programing experience and Knowledge of circuit design is a plus.
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