1.Path finding of library extraction modeling for leading edge tech nodes
2.Be the expert of library design kit and lead TSMC-EDA-IC design cooperation.
3.In-house library generation flow and/or utility development
4.RC parasitic extraction analysis and APR related analysis
1.We are looking for talents in the areas of VLSI design flow and chip sign-off process.
2.CS and EE master or PhD title is a must.
3.Familiarity with Knowledge of circuit design and analysis.
4.Proficient in algorithm programming and data analysis.
5.2+ years Python/Perl/TCL programming experience. is a plus.