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Layout Designer

Layout Designer
by Daniel Nenni on 09-07-2020 at 8:44 pm

  • Full Time
  • Canada

Website TSMC

Job Function:

TSMC Canada is looking for a layout designer to join its Layut team. The Designer will primarily be responsible for custom layout design. The Layout Engineer will be involved in R&D projects implemented no the world’s most advanced CMOS/FinFET processes (5nm and below). This will involve detailed implementation of the high speed and high density memory compilers and high-speed analog circuits. The successful candidate must demonstrate the ability to estimate, plan and coordinate layout work.



The successful candidate will perform custom layout implementing IC design in deep-submicron CMOS/FinFET. In addition, you will accomplish compact high performance memory and mixed signal layout: Memory, Mixed-Signal IP Blocks, I/O-PAD Ring, etc. using industry standard custom CAD tools, layout, DRC, LVS, RC Extraction etc. The Layout Designer will also be responsible for developing and verifying layout for memory compilers.


Hands-on working knowledge of CAD tools; expert user of at least one large CAD custom layout tool flow
Ability to deliver high quality layouts independently
Demonstrated knowledge writing scripts and software macros to enhance productivity as required
Some experience with an APR (automated place and route) ASIC backend flow is advantageous
Commitment to on-time delivery of top quality layouts
Ability to learn and adapt to new processes and design styles or constraints
Possess a disciplined and organized approach to work
A team player with good communication skills; excellent working knowledge of English (written and oral).
Ability to work well with teams in diverse locations (e.g. USA, Taiwan)
Additional Qualifications (Assets):

Scripting in Cadence Skill, Pearl, Compiler-Tiler, Linux
Verilog RTL ASIC design flow
Knowledge of physical design and layout and automatic place and route tools
Memory compiler layout design
Standard cell library layout design
High-speed Mixed-Signal, Analog or RF IC layout design
Layout database verification
Demonstrated experience in team leadership
FinFET experience is an asset

Engineering degree or technical diploma combined with some industry experience or at least 5 years’ relevant industry experience in custom memory layout

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