Job Location: Austin, TX
Hiring Manager: Sr. Manager, Power Management Design Program
Work with Analog and Digital team to define chip architecture
RTL development and verification (RTL and Gate level)
Static timing constraint generation and analysis/signoff
Lab evaluation and silicon debug
RTL design and verification flow development
Bachelor’s in Electrical Engineer or related field of study, plus 5+ years of relevant experience
Complete understanding of ASIC design flow from RTL to GDSII.
Familiarity with the Verilog language and simulators
A good understanding of analog functionality and exposure to analog IC design methods
Ability to solve problems using a systematic approach
Master’s in Electrical Engineer or related field of study and 10+ years digital/mixed signal ASIC architecture/design experience
RTL coding and synchronous/asynchronous digital skills
Experience with SystemVerilog
Knowledge of PLL, DLL, SerDes, DDR3, I2C and SPI
Simulation tools like NCsim, code coverage and debug tools
Synthesis, STA, Lint checkers, Clock domain crossing (CDC) checkers, Logic equivalence checking.
Scripting skills in Perl, Tcl, Python etc.
Demonstrated strong analytical and problem solving skills
Strong verbal and written communication skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery
Ability to work effectively in a fast-paced and rapidly changing environment
Ability to take the initiative and drive for results
TSMC Technology Inc. is an Equal Opportunity Employer.