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Library, Technology & Design Flow Co-Optimization Engineer

Library, Technology & Design Flow Co-Optimization Engineer
by Daniel Nenni on 07-15-2020 at 12:52 pm

Website TSMC

Hiring Manager:

Deputy Director, Design Methodology and Kit Development

Responsibilities:

Explore and demonstrate improved block PPA through library, technology, and design methodology and flow co-optimization on TSMC’s advanced process technologies (22nm/16nm/7nm/5nm).

Explore and innovate on TSMC’s design platform. Work towards co-optimizing standard cell library, design methodology and flows to show improved block performance.

Work closely with Design Flow team at company headquarters to gain a deep understanding of design methodology & flow, technology, capabilities and constraints.

Create several physical design implementations of standardized reference blocks to compare and contrast various tradeoffs between the different optimization techniques that will yield better overall gains in TSMC technology.

Root-cause design flow issues and independently develop Innovative solutions for design flows and design methodology challenges, validate and document solutions.

Work closely with EDA vendors to develop and demonstrate value in new design flows and strategies.

Internalize customer problems and have the grit to solve them in stipulated time constraints
May perform other duties as assigned including special projects and other administrative responsibilities.

Qualifications
Requirements:

M.S. or Ph.D. in Electrical or Computer Engineering with coursework in VLSI, CAD, and/or Digital Design.

Have strong background in how to library, technology, and design flows hand shake to create the final product and understand the knobs for better overall PPA.

5+ years of hands-on experience on RTL2GDSII or supporting SoC designs for the same including converging and taping out multi-Ghz SoC design partitions with multiple power domains on leading edge process technology (16nm/14nm/7nm or more advanced).

Be an expert user of Synopsys ICC /ICC2 and/or Cadence EDI/Innovus with strong working knowledge of Tcl, experience creating/modifying tech-files, developing & customizing design flows in placement, CTS, and routing to achieve an improved QOR.

Must have intellectual curiosity to debug/root cause of difficult problems and strong problem solving skills with an innovative mindset.

Prioritizing customer orientation with good communication skills are highly desirable.

tandard cell development understanding and cell PPA insights are added bonuses.

TSMC Technology Inc. is an Equal Opportunity Employer.

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To view the job application please visit tsmc.taleo.net.