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Staff Functional Safety Engineer

Staff Functional Safety Engineer
by Admin on 11-14-2023 at 8:05 pm

Website ArterisIP

Description

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

Do you want to contribute to the backbone of some of the world’s most popular SoCs?

As a Functional Safety Manager at Arteris, you will contribute to the planning, development, and compilation of required ISO26262 work products, with emphasis on process systematic capability aspects and Safety Analysis (FMEA, FMEDA, DFA). You will support the design team in the definition of appropriate safety mechanisms at both architecture and microarchitecture levels to comply with the Technical Safety Requirements. When required, you will support also fault injection simulations and activities by providing Functional Safety Verification Plan.

Key Responsibilities:

  • Be the IP team’s Functional Safety Manager.
  • Monitor the correct execution of the Functional Safety Life Cycle and support the IPs assessments.
  • Compilation of the IP Safety Plan, Safety Case and Safety Manual.
  • Lead Functional Safety Change Impact Analysis and support Change Management, Document Management and Configuration Management plan.
  • Lead the revision of the Safety Plan, Technical Safety Concept, and SEooC Assumptions.
  • Creation of Safety Analyses including FMEA, FMEDA and DFA, including preparing related safety reports.
  • Define or contribute to HW Functional Safety Requirements and Technical Safety Requirements. Work with architects, designers and design verification leaders to define and implement functional safety requirements in the design.
  • Support the IP team in selecting appropriated HW safety mechanisms for architecture and microarchitecture to comply with the HW Safety Requirements.
  • Traceability using Jama Software, Atlassian Jira and structured documents (like Adobe Structured FrameMaker).

Experience Requirements / Qualifications:

  • Strong process-oriented attitude and digital design and architecture skills to support Arteris IP functional safety products development and Assessment.
  • More than 5 years’ direct experience in Functional Safety applications (semiconductor).
  • More than 8 years’ experience or equivalent in SoC and system architecture, design, verification/validation. Solid micro-architectures understanding.
  • Deep knowledge of Functional Safety standards ISO 26262.
  • Working experience with industry-standard EDA tools (logic synthesis and coverage driven simulation).
  • Basic understanding of ARM architecture and AMBA Protocols such as APB, AXI, ACE, CHI will be considered a plus.
  • Direct experience with fault injection tools will be considered a plus.
  • English and French fluently

Education:

Master Degree in Computer Science or Functional Safety Engineering

About Arteris:

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.  Learn more at arteris.com

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