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STA Engineer

STA Engineer
by Admin on 05-03-2023 at 11:42 am

Website Mobiveil

Job Description

  • Experience in ASIC synthesis
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF (Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language


  • RTL
  • HDL
  • perl
  • TCL
  • ASIC
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To view the job application please visit mobiveil.com.

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