Website Flex Logix
Flex Logix is the leading provider of reconfigurable computing technology for both AI inference and eFPGA IP solutions. Our offerings push the leading edge of hardware, software and system design; pioneering new approaches to important problems.
- Our InferX X1 is the industry’s most-efficient AI edge inference accelerator that brings AI to the masses in high-volume applications by providing a new silicon efficient dynamic logic paradigm for inference processing. InferX achieves GPU-level inference performance with a fraction of the die area and memory footprint.
- Our EFLX embedded FPGA (eFPGA) IP enables any SOC design to flexibly handle changing protocols, standards, algorithms, and customer requirements and enables reconfigurable accelerators that speeds key workloads up to 1000x compared to a general purpose processor. EFLX eFPGA is available in a wide range of process technologies and supports designs ranging from low cost microcontrollers to 5G baseband processing solutions.
Flex Logix is looking for passionate STA Design Engineer to contribute to delivering high standard EFLX (embedded FPGA) and nnMAX (Inference accelerator) cores in advanced technology nodes. You will work closely with the Architect, Designer and Implementation team in developing IPs. You will work on setting up flows, writing timing constraints, running synthesis, fixing timing paths, and timing signoff.
- Deploy synthesis and STA flows with industry standard tools.
- Setting up synthesis methodology to optimize design.
- Writing and validating timing constraints.
- Signoff timing closure.
- Generating timing model (LIB) for IPs.
- Develop and validate high performance low power clock network guidelines.
- Generate and Implement ECOs to fix timing, noise.
- Participate in establishing CAD and Design methodologies for correct construction designs.
- 7+ years of Synthesis and Static Timing Analysis experience on IP and/or SOC designs.
- Deep Knowledge about industry standards and practices in Synthesis, including Physically aware synthesis and Static Timing Analysis.
- Power user of industry standard STA & Synthesis tools.
- Hands-on experience in Timing Constraints / SDC.
- Deep understanding of timing corners, operating modes, OCV, cross-talk, noise, signoff criteria.
- Hands-on experience in Logic equivalence Checking / Formal Verification.
- Familiar with Functional and Timing ECO techniques.
- Familiar with DFT functionality and implementation.
- Shown Knowledge of Basic Architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes.
- Deep Understanding of scripting languages such as Perl/python/Tcl.
- Familiar with digital implementation flows and methodology.
- Bachelor’s or Master’s Degree in EE/CS required.
- RTL design.
- Physical Design / Implementation.
- Physical Verification.
- Power optimization.
We are looking for passionate team members, to be part of an aggressive, venture-backed startup team that is changing chip architecture. Must be entrepreneurial, innovative problem solver, willing to work hard and have fun.
As we continue to grow and expand our company, we are hiring for all office locations. You must live near one of our main offices located in: Mountain View (CA), Austin (TX), Chicago (IL) or Vancouver (BC). We offer a flexible work schedule.
You must have US citizenship or permanent residency (“green card”) or hold a current H1-B visa to work in United States.
Flex Logix recruits, employs, trains, compensates and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.
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To view the job application please visit flex-logix.com.