Sr. Physical Design Engineer
Website Alchip
Work content
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place & route, clock tree synthesis, timing sign off and physical verification.
2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist.
3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge.
4. Work with manager to achieve assigned tape out target.
Other conditions
1. Bachelor or MS degree in EE or related.
2. Able to independently complete block level design from netlist, floor plan, synthesis, CTS, APR, STA and PV.
3. Experience of working on top level design with chip level floor plan is a plus.
4. Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibre for physical design engineer and Mentor/Synopsys DFT tools for DFT Engineer.
5. Familiar with TCL/Perl scripting and design automation.
6. Fluent English is a plus.
7. Experience in 28/40nm design is a plus.
Has ASML Reached the Great Wall of China