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Sr Design Verification Engineer

Sr Design Verification Engineer
by Admin on 04-08-2022 at 11:13 am

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Sr Design Verification Engineer


  • Create test-plan and execute until all features are verified with functional and code coverage
  • Create Test scenarios, generate tests using and debug failures on existing testbenches
  • Debug failing tests and root-cause failures to identify suspected part of the design

Must have Skills:

  • MSEE/MSCS/MSCE degree or BSEE/BSCS/BSCE degree
  • Experience range 5-15+ years
  • Experience with verification methodologies like UVM and System Verilog (SV)
  • Expertise in Constrained Radom Verification Environment development
  • Expertise in deriving Feature List, Test-plan, Erroneous, Directed and Random Test-suit development and debugging
  • Expertise in deriving Functional coverage matrix, Assertion Matrix etc
  • Should be capable to achieve closure on Functional and Code coverage, building exclusions and refinements
  • Should have good command in managing Failing regression triage and debugging / UVM environment debugging / testcase debugging
  • Expertise in IP as well as SOC verification

Good to have skills:

  • Experience with ARM bus protocols like AMBA, AXI, AHB, APB
  • Object Oriented Programming knowledge
  • Scripting tools like Python, Shell
  • Bonus if the candidate is familiar with GIT [Version Control System]
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