Solutions Engineer, Sr I

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. We are looking for Senior DFT Solutions Engineer to join our team. Does this sound like a good role for you? The successful candidate will be responsible for designing, developing, troubleshooting, debugging software programs. Develops software tools including operating systems, compilers, routers, networks, utilities, databases and internet-related tools Establishes hardware compatibility and/or influences hardware design.

Sr. DFT Solutions Engineer:  We’re looking for DFT Solutions Engineer to join our team.   The engineer works in a project-oriented environment to deliver complex DFT flows and methodologies across varying industry segments like Autonomous Transportation, Mission critical AI, High performance computing and Mobile networking.   The engineer also interacts with the customers to assess their methodologies and flows and provides feedback to the Test Product business unit on customer DFT requirements.  The engineer also interfaces with the Solutions architect and Software R&D team, provides feedback to the Test product business unit on customer specifications and requirements.

Responsibilities may include a subset or all of the following:

• Consultation for test solutions during design planning/budgeting.
• Scan stitching, core wrapping, test point insertion etc through design compiler and fusion compiler flows at Synopsys
• Test methodology design rules checking during RTL coding stages.
• Implementation of design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models
• Architects and implements solutions for built-in self-test (Memory and Reason BIST) circuitry to test devices in the field.
• Participations in customer’s design and flow reviews.
• Diagnostics study and debug.
• Provides methodologies for test automation flow integration with design planning, RTL analysis, logic synthesis, physical design, and sign-off verification tools (static timing, simulation, formal verification).
• Develops white papers on methodology and other documentation as may be required for projects.
• Provides technical support/expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios.

Key Qualifications

• B.E or M.S. in EE,Microelectronics or related field
• At lease 6 years of relevant work experience in DFT
• Courses taken in circuit design, digital IC design
• Excellent understanding of RTL design
• Excellent knowledge in scripting, TCL and Perl are preferred.
• Ability and desire to dig into and solve complex parallel programming challenges
• Understanding of concurrent execution topics and inter-process communication
• Excellent analysis and problem-solving skills
• Excellent verbal and written communication skills
• Excellent understanding of the Linux OS and tools
• Ability to produce design documents detailing product requirements and solution elements
• Desire to learn and explore new technologies
• Excellent communication and presentations skills are mandatory. Listening, understanding, and interpreting the customer requirements are a key part of the communications skill set. Good technical problem-solving skills are a must.
• Design and verification experience are a plus.
• Understand Design-for-testing concept is a plus

Preferred Experience

• Familiar with general IC design flow
• Familiar with Verilog coding style and best practices
• Familiar with VLSI implementation flow
• Excellent English communication skill
• Proficient user of Perl or TCL is preferred