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Memory Subsystem Verification Engineer

Memory Subsystem Verification Engineer
by Daniel Nenni on 07-05-2020 at 11:21 am

Website SiFive SiFive

As an experienced Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.

This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works.

What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures.

This role is for the verification of our CPU memory sub-system including caches, virtual memory, and system connections that use AMBA and TileLink protocols.

LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.

Responsibilities

Architect test methodologies applicable to a wide range of CPU and SoC designs for CPU memory sub-systems including Load-Store unit, various levels of caches, memory virtualization and industry standard bus protocols (e.g. AMBA and TileLink).

Understand CPU caches and SoC designs from an architectural level and create effective verification strategies for these designs.

Build test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.

Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.

Provide technical leadership for verification engineers and coordinate technical teams to execute our verification strategies to meet program goals.

Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.), especially in hands-on testbench development and test suite generation.

Solid understanding of CPU and SoC memory architecture including Load-Store unit, various levels of caches, cache coherence protocols, virtual memory, bus interface units, and memory controllers.

Experience with industry standard system bus protocols (e.g. AMBA AXI, AHB, APB) is preferred. Knowledge of TileLink is a plus.
A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).

Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.

Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).

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To view the job application please visit jobs.lever.co.