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RTL Design Engineer – Cache Subsystem

RTL Design Engineer – Cache Subsystem
by Daniel Nenni on 09-12-2020 at 5:56 pm

  • Full Time
  • Sam Mateo, CA
  • Applications have closed

Website SiFive SiFive


Architect, design and implement new cache subsystems in SiFive’s RISC-V CPU core generators and enhance features and performance in existing ones.

Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Perform initial sandbox verification, and work with design verification team to create and execute detailed verification test plans.

Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.

Collaborate with performance modeling team for performance exploration and optimization to meet performance goals.


5+ yrs of recent industry experience in high-performance, energy-efficient CPU cache subsystem designs.

Expertise in multi-level coherent CPU cache architectures and designs.

Knowledge of RISC-V architecture is a plus.
Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.

Experience with Scala and/or Chisel is a plus.
Attention to detail and a focus on high-quality design.

Ability to work well with others and a belief that engineering is a team sport.

Knowledge of at least one object-oriented and/or functional programming language.

Background of successful CPU cache subsystem development from architecture through tapeout.
BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

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