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RISC-V FPGA Verification Engineer

RISC-V FPGA Verification Engineer
by Daniel Nenni on 09-12-2020 at 6:29 pm

Website SiFive SiFive

Responsibilities

Bring up Silicon designs on FPGA platforms, root causing design, test and emulator environment issues failures.

Collaborate with cross-functional teams on developing and implementing emulation strategy based on product goals.

Establish key hardware and software on emulation to establish readiness for silicon and software bring-up.

Requirements

A minimum of 3 years of direct FPGA experience, including system testing and debug using FPGAs
Strong FPGA platform based development and testing experience

Familiarity with and/or ability to learn languages and methodologies that are not part of the industry-standard approach to verification (Scala, Chisel, etc.)

A conscientious and thorough approach to Design Verification

Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same

A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure)

Good interpersonal skills to listen to diverse points of view and influence people from different disciplines

An unwavering dedication to product quality

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