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Verification Engineer

Verification Engineer
by Daniel Nenni on 07-05-2020 at 11:28 am

Website SiFive SiFive

As an experienced Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.

This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works.

What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures.

Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.

Responsibilities

Understand CPU and SoC designs from an architectural level and create effective verification strategies for these designs.

Create test plans and test environments.

Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.

Develop checkers and assertions to verify the design.

Write functional coverage, analyze both code and functional coverage, and close coverage holes.

Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.).

Solid understanding of CPU and SoC architectures, or a strong desire and ability to learn same.

A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).

Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.

Excellent debug skills.

Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).

Apply for job

To view the job application please visit jobs.lever.co.