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Memory Subsystem Verification Engineer

Memory Subsystem Verification Engineer
by Daniel Nenni on 08-17-2020 at 6:26 pm

  • Full Time
  • Austin, Texas
  • Applications have closed

Responsibilities

Architect test methodologies applicable to a wide range of CPU and SoC designs for CPU memory sub-systems including Load-Store unit, various levels of caches, memory virtualization and industry standard bus protocols (e.g. AMBA and TileLink).
Understand CPU caches and SoC designs from an architectural level and create effective verification strategies for these designs.
Build test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
Provide technical leadership for verification engineers and coordinate technical teams to execute our verification strategies to meet program goals.
Collaborate closely with the design team on feature specifications, test plans and failure analysis.
Requirements

7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.), especially in hands-on testbench development and test suite generation.
Solid understanding of CPU and SoC memory architecture including Load-Store unit, various levels of caches, cache coherence protocols, virtual memory, bus interface units, and memory controllers.
Experience with industry standard system bus protocols (e.g. AMBA AXI, AHB, APB) is preferred. Knowledge of TileLink is a plus.
A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).
Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off; health, vision, and dental benefits; 401(k) plan; employee stock option program, and much more.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you.

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