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SerDes FAE

SerDes FAE
by Admin on 05-08-2023 at 3:30 pm


  • Build and develop relationships with customers, manage customer expectations to optimize customer satisfaction.
  • Follow up customers’ questions on SerDes IP.
  • Track and update JIRA support tracking management system to meet SLA.
  • Verilog model integration and simulation.
  • GDS physical integration and floorplan design.
  • DFT integration.
  • Timing closure.
  • SerDes EVB testing.
  • Firmware integration.
  • Post-Silicon bring up.
  • Post-Silicon validation.
  • Analyze and identify characteristics of requirements.


  • Bachelor degree or above majored in Electrical Engineering/Computer Science/ Communication Engineering and related.
  • At least 5 years experience from SerDes product FAE or PM of semiconductor company; chip design experience is preferred.
  • Familiar with SerDes or IC design/verification/manufacturing flow, familiar with software and hardware of SerDes or chip application.
  • Deeply understanding on high-speed IO of advanced process (16nm/7nm/5nm), high-speed SerDes(28G/56G/112G), PCI Express, or deeply understanding on advanced process IP/chip design and advanced package technology.
  • Deep understanding or relevant experience on SerDes application and its technology supply chain, IP partners and customers are preferred.
  • Excellent communication, organization and coordination ability, good project management ability and self-driving ability.
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