Webinar PQC SemiwikiV4

Senior Verification Engineer

Senior Verification Engineer
by Admin on 09-20-2023 at 4:14 pm

  • Full Time
  • Noida, India
  • Applications have closed

Website Synopsys

Job Description and Requirements

We are seeking a Digital Verification Engineer who will be involved for functional verification of High Speed interface IPs.  A dynamic personality with eager to learn, drive Pre-silicon verification activities, good knowledge of digital design & HDL implementation.

Job Description

  • Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards
  • IP/design blocks/Firmware Specification study and build/update verification plans as well as the test cases
  • Build/update functional verification environments to execute the test plans
  • Implement checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs) as per the verification plan needs
  • Performing simulation, random and direct stimulus development and coverage review
  • Work closely with digital designers for debug and achieve the desired coverage


  • B.Tech/M.Tech with 3+ years of relevant experience
  • Understanding of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System Verilog
  • Experience with System Verilog Assertions, code and functional coverage implementation and review
  • Scripting and automation using TCL/PERL/Python
  • Excellent debug and diagnostic skills
Share this post via: