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Senior Validation Engineer

Senior Validation Engineer
by Admin on 10-18-2022 at 3:33 pm

Website ArterisIP

Responsibilities:

  • Define validation plans in collaboration with the Product Owner and software development teams.
  • Set up test examples, reference files and scripts for automated execution of the test suite.
  • Qualify the expected inputs and outputs (RTL, documentation, etc.) of our software using various CAD tools (simulators, formal proof, etc.).
  • Validate the GUI and APIs used by our customers.

Experience, Requirements and Qualifications:

  • 3+ years of design and/or verification experience and a plus in interconnect verification experience.
  • Proficiency in at least one scripting language (TCL or Python ideally).
  • Knowledge of the IP-XACT XML standard is a plus.
  • Strong skills in RTL (Verilog).
  • Very rigorous.

Education:

  • Master’s degree in EE (Electrical Engineering), CS (Computer Science), or equivalent preferred.
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To view the job application please visit www.arteris.com.

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