Senior Validation Engineer

ARTERIS IP is the world leader in SoC and NoC systems, with nearly 200 employees in France and abroad.

Our technology is used by the most innovative electronic systems providers, ranging from AI to automotive, cell phones, IoT, cameras, SSD controllers and servers.

To support our growth, we are looking for a Senior Validation Engineer at Arteris IP M/F.

In this position, you will become a key player in the validation of our System on Chip (SoC) RTL design environment.

We work with an agile methodology, in continuous integration, and use GIT, JIRA and Confluence.

Responsibilities:

• Define validation plans in collaboration with the Product Owner and software development teams.
• Set up test examples, reference files and scripts for automated execution of the test suite.
• Qualify the expected inputs and outputs (RTL, documentation, etc.) of our software using various CAD tools (simulators, formal proof, etc.).
• Validate the GUI and APIs used by our customers.

Experience, Requirements and Qualifications:

• 3+ years of design and/or verification experience and a plus in interconnect verification experience.
• Proficiency in at least one scripting language (TCL or Python ideally).
• Knowledge of the IP-XACT XML standard is a plus.
• Strong skills in RTL (Verilog).
• Very rigorous.

Education:

• Master’s degree in EE (Electrical Engineering), CS (Computer Science), or equivalent preferred.