Senior Staff Hardware Design Engineer – Advanced Engineering

Do you want to contribute to the backbone of some of the world’s most popular System on Chips?

As a Senior Staff Hardware Design Engineer at Arteris, you will have a leading role in the development of next generation of Arteris IP solutions, in charge of the architecture and the design of extremely configurable digital circuits.

The candidate will be responsible to architect and design the next generation of Arteris interconnect and system IPs for on chip and inter die communications, within best-in class area, power, performance and safety requirements.

We intend to revolutionize the way to design SoC, and we are looking for engineering talents willing to expose themselves to new design methodologies and ready to grow his skills towards both hardware and software-based development.

The position will be ideally staffed in Sophia Antipolis, France, as part of the advanced engineering team.

You will join a proven-successful company and be able to shape the future of System on Chip design.

Key Responsibilities:

• Lead the HW design of next generation Network on Chip configurable IP blocks in a powerful programmable description language
• Design all the new elements of the NoC (Switch, Sockets, protocol, transport, …) and build a best-in-class communication systems for coherent & non-coherent protocols
• Contribute to the verification methodology and regression environment
• Communicate with software and documentation teams to ensure product cohesion and overall performances
• Maintain and enhance the design development flow methodology to increase automation

Experience Requirements / Qualifications:

Required:

• 8+ years of experience in HW SoC development
• Proficient with HW description language (Verilog, System Verilog)
• Knowledge of bus protocol architectures (AMBA, OCP)
• Excellent problem solving, strong communication and teamwork skills,
• Self-driven, able to work with minimum supervision.

Desired:

• Experience with digital HW generators, methodology and concept
• Know Object Oriented Programable languages (C++, JAVA)
• Knowledge of interconnect technology and cache coherent system

Education Requirements:

• PhD or master’s degree in Computer Sciences or related field.