Senior Staff Design Verification Engineer

Description

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

Senior Staff Design Verification Engineer with Arteris, Inc. d/b/a Arteris IP (Austin, TX)

Design and deliver interconnect and memory hierarchy solutions. Conduct advanced UVM test bench development and debugging. Define, document, develop, and execute RTL verification tests and coverage. Support and improve verification process, methodology, and metrics on System on Chip (SoC). Architect, define, and develop advanced UVM test benches using System Verilog, JavaScript, and JSON. Architect, define, and develop SoC test benches to perform functional verification of: SoC embedded RISC/DSP processors; communications; and networking ASIC hardware (interconnect) cache coherency at IP, subsystem, and SoC and system architecture for server processors and applications. Analyze code coverages for design stress levels. Work on complex SoC projects from test bench development to verification closure.  Conduct performance verification and power-aware verification. Conduct triage regressions. Debug RTL designs in Verilog and SystemVerilog. Use Electronic Design Automation tools to debug regression and simulation issues to improve quality of the ASIC design.

Telecommuting permitted. Applicants must live with reasonable commuting distance. Position reports directly to 9601 Amberglen Blvd., Ste 117, Austin, TX 78729.

Requires a Bachelor’s or Master’s in Electronic Engineering, Computer Science, Computer Information Systems, or related field. Experience is required (5 years with Bachelor’s or 3 years with Master’s). Must have some experience in each of the following skills: Verilog & System Verilog; UVM; VCS and QUESTASIM EDA; OOP, Bash, Jenkins, Questa Visualizer, Synopsys DVE, Verdi, Questa VSIM, and Questa Covercheck to develop and implement test plans, debug, and execute regression setups and coverage closures; and Arm AMBA protocols: APB, AHB, AXI, AXI Lite, ACE and CHI.

Salary: $175,000 – $195,000 / year

About Arteris:

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.  Learn more at arteris.com.