Senior SERDES Circuit Design Engineer

In this position you will play a key technical leadership role in developing advanced mixed signal circuits for low power, high-speed, Fin-FET SERDES macros to be used in numerous products from high performance data center SoCs to low power consumer SoCs. You will join a highly collaborative team, and your success will have a significant impact on our products.

Candidates should have an interest in all the “Key Qualifications” listed below, and significant experience in some of them. Candidates who have less than the required experience should apply to the non Senior position.

Key Qualifications

• At least 5 years of hands-on circuit design for high-speed SERDES.
• Knowledge of SERDES architecture.
• Strong understanding of analog design fundamentals.
• Mixed signal, analog and digital circuit design in advanced FinFET processes.
• Knowledge of SERDES circuit implementation such as:
  • Analog front-end design for RX
  • Equalization design: CTLE, VGA, DFE
  • High speed sampler design
  • Adaptation algorithms for system level simulations
  • High speed ADC
  • High Speed Clocking
  • TX Serializer and Driver Design
• Signal Integrity.
• Ability to operate lab equipment such as J-BERT, high-speed scopes, etc.
• Ability to provide customer support.

Description

• Contribute to the circuit design of advanced Fin-FET SERDES macros.
• Design of different circuit blocks: CTLE, DFE, data samplers, high-speed ADC, driver, PLL, clocking, CDR, etc.
• Layout supervision and post-layout analysis.
• Design review and documentation.
• Silicon bring-up, debug, and evaluation.
• Supervision and mentoring of junior level circuit design engineers.

Education

MSEE / Ph.D. in Electrical Engineering

Base Salary Ranges:

• 3 – 5 years experience: $150,000.00 – $215,000.00
• 6 – 10 years experience: $180,000.00 – $300,000.00

We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.